Commits · e5f4a2c5b54e058e52c42eeb9f0af456e34da40f · streichg / Finn · GitLab

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May 23, 2023
- Add missing simulation fileset. · e5f4a2c5
  Thomas B. Preußer authored 1 year ago
  
  e5f4a2c5
May 16, 2023
- Polish interface attributes. Use all-lower-case finn library name like other modules. · f15c00d8
  Thomas B. Preußer authored 1 year ago
  
  f15c00d8
May 09, 2023
- Yet another fix of the address width expression for IP integrator. · 0bb289ca
  Thomas B. Preußer authored 1 year ago
  
  0bb289ca
May 05, 2023
- [rtllib] Linting of updated tcl script · 96277dba
  auphelia authored 1 year ago
  
  96277dba
- Have IPI recompute AXI-lite address width according to user-defined memory layout. · 06ab3ecc
  Thomas B. Preußer authored 1 year ago
  
  06ab3ecc
Apr 24, 2023
- [rtllib] linting on tcl script · cd8c6817
  auphelia authored 1 year ago
  
  cd8c6817
Apr 21, 2023
- [finn-rtllib] Re-instantiate FIFO rtl implementation · 763d876e
  auphelia authored 1 year ago
  
  763d876e
- Renaming configuration interface to s_axilite. · c179c0cd
  Thomas B. Preußer authored 1 year ago
  
  c179c0cd
- Prepare for memstream instantiation as an IP core. · 1155ac40
  Thomas B. Preußer authored 1 year ago
  
  1155ac40
Apr 18, 2023
- Adding FINN instantiation template for revised memstream module. · 39e4c313
  Thomas B. Preußer authored 1 year ago
  
  39e4c313
- Streamlined memstream module tested with random interleaved parameter readback. · 9ee018ff
  Thomas B. Preußer authored 1 year ago
  
  9ee018ff
Mar 23, 2023
- [SWG] Incorporate minor comments on Verilog code · 24bd1907
  Felix Jentzsch authored 2 years ago
  
  24bd1907
Mar 14, 2023
- [SWG] Move common modules to static source file · 40eb5c7d
  Felix Jentzsch authored 2 years ago
  
  40eb5c7d
Jan 27, 2023
- [SWG] Adjust resource estimates, set_folding · 7f4b20f6
  Felix Jentzsch authored 2 years ago
  
  7f4b20f6
Dec 01, 2022
- [RTL SWG] Rework parallel-output implementation style · 0fb57af5
  Felix Jentzsch authored 2 years ago
  
  0fb57af5
Oct 27, 2022
- [SWGG] improve HDL code · 3d002f7e
  Felix Jentzsch authored 2 years ago
  
  3d002f7e
Oct 24, 2022
- [SWGG] incorporate Yaman's changes + small fixes · 83550c64
  Felix Jentzsch authored 2 years ago
  
  83550c64
Oct 21, 2022
- [Pad] use contiguous, 4b-aligned config addrs for RTL variant · 79d64148
  Yaman Umuroglu authored 2 years ago
  
  79d64148
- [SWGG] rename dynamic cfg interface to s_axilite · 6e91fcd6
  Yaman Umuroglu authored 2 years ago
  
  6e91fcd6
Oct 17, 2022
- [Pad] typo fix in template · 835ba0fa
  Yaman Umuroglu authored 2 years ago
  
  835ba0fa
- [Pad] more changes to RTL inst template for Verilog compatibility · 43a37155
  Yaman Umuroglu authored 2 years ago
  
  43a37155
Oct 16, 2022
- [Pad] switch top-level template SystemVerilog->Verilog · cb0bf3cb
  Yaman Umuroglu authored 2 years ago
  
  this keeps Vivado happy for interface inference for blocks
  cb0bf3cb
Oct 14, 2022
- Add sanity checking for generics. · ff348d47
  Thomas B. Preußer authored 2 years ago
  
  ff348d47
Oct 13, 2022
- [Pad] update fmpadding_rtl template · e2cc28d3
  Yaman Umuroglu authored 2 years ago
  
  e2cc28d3
- Added capability to custom-initialize dynamic parameter registers upon design configuration. · ba9a45f0
  Thomas B. Preußer authored 2 years ago
  
  ba9a45f0
Oct 12, 2022
- [FMPadding] conversion, inst template, CustomOp for FMPadding_rtl · 4f4bec7a
  Yaman Umuroglu authored 2 years ago
  
  4f4bec7a
- Added AXI-Light adapter to dynamically-sized feature map padding. · ee2748a2
  Thomas B. Preußer authored 2 years ago
  
  ee2748a2
- First prototype for dynamically sized FM padding. · cba8536a
  Thomas B. Preußer authored 2 years ago
  
  cba8536a
Oct 11, 2022
- Added AXI-Light adapter to dynamically-sized feature map padding. · 03ccfb5e
  Thomas B. Preußer authored 2 years ago
  
  03ccfb5e
Oct 10, 2022
- First prototype for dynamically sized FM padding. · c52ab50d
  Thomas B. Preußer authored 2 years ago
  
  c52ab50d
Oct 04, 2022
- FIFO] bugfix post-reset ibp condition on Q_srl · 1a4166c9
  Yaman Umuroglu authored 2 years ago
  
  1a4166c9
Sep 27, 2022
- [FIFO] SystemVerilog -> Verilog fix in Q_srl.v · a8d3fb6c
  Yaman Umuroglu authored 2 years ago
  
  a8d3fb6c
Sep 26, 2022
- [FIFO] SystemVerilog -> Verilog fix in Q_srl.v · dc830f11
  Yaman Umuroglu authored 2 years ago
  
  dc830f11
Sep 22, 2022
- [Style] Minor style fixes to added components · fdb00bb5
  auphelia authored 2 years ago
  
  fdb00bb5
- Working initial implementation · ecb5a7e3
  Felix Jentzsch authored 2 years ago
  
  ecb5a7e3
Sep 19, 2022
- [FIFO] add hw maxcount tracking to rtl FIFOs with opt attribute · e8f7c756
  Yaman Umuroglu authored 2 years ago
  
  e8f7c756
Sep 16, 2022
- Address reviewer comments · 5e0e8989
  Felix Jentzsch authored 2 years ago
  
  5e0e8989
Sep 09, 2022
- Move parallel impl. to different branch, cleanup · 57f9fecd
  Felix Jentzsch authored 2 years ago
  
  57f9fecd
Aug 24, 2022
- Restructure, basic resource estimation · f46e2d0a
  Felix Jentzsch authored 2 years ago
  
  f46e2d0a
Jul 14, 2022
- Revert "Merge pull request #637 from Xilinx/dev" · 963fde53
  auphelia authored 2 years ago
  
  This reverts commit fe4a150c, reversing changes made to c98c2211.
  963fde53