[Pad] use contiguous, 4b-aligned config addrs for RTL variant

finn-rtllib/fmpadding/hdl/axi2we.sv

@@ -57,7 +57,7 @@ module axi2we #(
 	// Reading tied to all-ones
 	input	       s_axilite_ARVALID,
 	output	       s_axilite_ARREADY,
-	input	[3:0]  s_axilite_ARADDR,
+	input	[ADDR_BITS-1:0]  s_axilite_ARADDR,
 
 	output	        s_axilite_RVALID,
 	input	        s_axilite_RREADY,

finn-rtllib/fmpadding/hdl/fmpadding.sv

@@ -53,7 +53,7 @@ module fmpadding #(
 
 	// Parameter Configuration ----------
 	input	logic         we,
-	input	logic [ 2:0]  wa,
+	input	logic [ 4:0]  wa,
 	input	logic [31:0]  wd,
 
 	//- AXI Stream - Input --------------
@@ -125,13 +125,12 @@ module fmpadding #(
 	always_ff @(posedge clk) begin
 		if(we) begin
 			unique case(wa)
-			0:  XOn  <= wd;
-			1:  XOff <= wd;
-			2:  XEnd <= wd;
-
-			4:  YOn  <= wd;
-			5:  YOff <= wd;
-			6:  YEnd <= wd;
+			0*4:  XOn  <= wd;
+			1*4:  XOff <= wd;
+			2*4:  XEnd <= wd;
+			3*4:  YOn  <= wd;
+			4*4:  YOff <= wd;
+			5*4:  YEnd <= wd;
 
 			default:  assert(0) else begin
 				$error("Illegal write address.");

finn-rtllib/fmpadding/hdl/fmpadding_axi.sv

@@ -55,7 +55,7 @@ module fmpadding_axi #(
 	// Writing
 	input	       s_axilite_AWVALID,
 	output	       s_axilite_AWREADY,
-	input	[2:0]  s_axilite_AWADDR,
+	input	[4:0]  s_axilite_AWADDR,
 
 	input	        s_axilite_WVALID,
 	output	        s_axilite_WREADY,
@@ -69,7 +69,7 @@ module fmpadding_axi #(
 	// Reading
 	input	       s_axilite_ARVALID,
 	output	       s_axilite_ARREADY,
-	input	[3:0]  s_axilite_ARADDR,
+	input	[4:0]  s_axilite_ARADDR,
 
 	output	        s_axilite_RVALID,
 	input	        s_axilite_RREADY,
@@ -89,9 +89,9 @@ module fmpadding_axi #(
 
 	// AXI-Lite Adapter
 	uwire         we;
-	uwire [ 2:0]  wa;
+	uwire [ 4:0]  wa;
 	uwire [31:0]  wd;
-	axi2we #(.ADDR_BITS(3)) axilight_adapter (
+	axi2we #(.ADDR_BITS(5)) axilight_adapter (
 		.ap_clk, .ap_rst_n,
 
 		.s_axilite_AWVALID, .s_axilite_AWREADY, .s_axilite_AWADDR,

finn-rtllib/fmpadding/hdl/fmpadding_template.v

@@ -40,7 +40,7 @@ input	ap_rst_n,
 // Writing
 input	       s_axilite_AWVALID,
 output	       s_axilite_AWREADY,
-input	[2:0]  s_axilite_AWADDR,
+input	[4:0]  s_axilite_AWADDR,
 
 input	        s_axilite_WVALID,
 output	        s_axilite_WREADY,
@@ -54,7 +54,7 @@ output	[1:0]  s_axilite_BRESP,
 // Reading
 input	       s_axilite_ARVALID,
 output	       s_axilite_ARREADY,
-input	[3:0]  s_axilite_ARADDR,
+input	[4:0]  s_axilite_ARADDR,
 
 output	        s_axilite_RVALID,
 input	        s_axilite_RREADY,

src/finn/custom_op/fpgadataflow/fmpadding_rtl.py

@@ -284,12 +284,12 @@ class FMPadding_rtl(HLSCustomOp):
         idt = self.get_input_datatype()
         code_gen_dict = self.get_template_values(ifm_dims, pads, chans, simd, idt)
         config = {
-            "XON": (0, (code_gen_dict["INIT_XON"])),
-            "XOFF": (1, (code_gen_dict["INIT_XOFF"])),
-            "XEND": (2, (code_gen_dict["INIT_XEND"])),
-            "YON": (4, (code_gen_dict["INIT_YON"])),
-            "YOFF": (5, (code_gen_dict["INIT_YOFF"])),
-            "YEND": (6, (code_gen_dict["INIT_YEND"])),
+            "XON": (0 * 4, (code_gen_dict["INIT_XON"])),
+            "XOFF": (1 * 4, (code_gen_dict["INIT_XOFF"])),
+            "XEND": (2 * 4, (code_gen_dict["INIT_XEND"])),
+            "YON": (3 * 4, (code_gen_dict["INIT_YON"])),
+            "YOFF": (4 * 4, (code_gen_dict["INIT_YOFF"])),
+            "YEND": (5 * 4, (code_gen_dict["INIT_YEND"])),
         }
         return config