[Pad] more changes to RTL inst template for Verilog compatibility

finn-rtllib/fmpadding/hdl/fmpadding_template.v

@@ -32,9 +32,9 @@
 module $TOP_MODULE_NAME$(
 //- Global Control ------------------
 (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V:s_axilite" *)
-input	logic  ap_clk,
+input	ap_clk,
 (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V:s_axilite" *)
-input	logic  ap_rst_n,
+input	ap_rst_n,
 
 //- AXI Lite ------------------------
 // Writing
@@ -62,14 +62,14 @@ output	[31:0]  s_axilite_RDATA,
 output	[ 1:0]  s_axilite_RRESP,
 
 //- AXI Stream - Input --------------
-output	logic  in0_V_TREADY,
-input	logic  in0_V_TVALID,
-input	logic [$STREAM_BITS$-1:0]  in0_V_TDATA,
+output	in0_V_TREADY,
+input	in0_V_TVALID,
+input	[$STREAM_BITS$-1:0]  in0_V_TDATA,
 
 //- AXI Stream - Output -------------
-input	logic  out_V_TREADY,
-output	logic  out_V_TVALID,
-output	logic [$STREAM_BITS$-1:0]  out_V_TDATA
+input	out_V_TREADY,
+output	out_V_TVALID,
+output	[$STREAM_BITS$-1:0]  out_V_TDATA
 );
 
 
@@ -90,23 +90,23 @@ $TOP_MODULE_NAME$_impl
 (
  .ap_clk(ap_clk),
  .ap_rst_n(ap_rst_n),
- .s_axilite_AWVALID,
- .s_axilite_AWREADY,
- .s_axilite_AWADDR,
- .s_axilite_WVALID,
- .s_axilite_WREADY,
- .s_axilite_WDATA,
- .s_axilite_WSTRB,
- .s_axilite_BVALID,
- .s_axilite_BREADY,
- .s_axilite_BRESP,
- .s_axilite_ARVALID,
- .s_axilite_ARREADY,
- .s_axilite_ARADDR,
- .s_axilite_RVALID,
- .s_axilite_RREADY,
- .s_axilite_RDATA,
- .s_axilite_RRESP,
+ .s_axilite_AWVALID(s_axilite_AWVALID),
+ .s_axilite_AWREADY(s_axilite_AWREADY),
+ .s_axilite_AWADDR(s_axilite_AWADDR),
+ .s_axilite_WVALID(s_axilite_WVALID),
+ .s_axilite_WREADY(s_axilite_WREADY),
+ .s_axilite_WDATA(s_axilite_WDATA),
+ .s_axilite_WSTRB(s_axilite_WSTRB),
+ .s_axilite_BVALIDs_axilite_BVALID(),
+ .s_axilite_BREADY(s_axilite_BREADY),
+ .s_axilite_BRESP(s_axilite_BRESP),
+ .s_axilite_ARVALID(s_axilite_ARVALID),
+ .s_axilite_ARREADY(s_axilite_ARREADY),
+ .s_axilite_ARADDR(s_axilite_ARADDR),
+ .s_axilite_RVALID(s_axilite_RVALID),
+ .s_axilite_RREADY(s_axilite_RREADY),
+ .s_axilite_RDATA(s_axilite_RDATA),
+ .s_axilite_RRESP(s_axilite_RRESP),
  .s_axis_tready(in0_V_TREADY),
  .s_axis_tvalid(in0_V_TVALID),
  .s_axis_tdata(in0_V_TDATA),