Yet another fix of the address width expression for IP integrator.

finn-rtllib/memstream/component.xml

@@ -249,6 +249,10 @@
           <spirit:name>ASSOCIATED_BUSIF</spirit:name>
           <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_BUSIF">m_axis_0:s_axilite</spirit:value>
         </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.FREQ_TOLERANCE_HZ">-1</spirit:value>
+        </spirit:parameter>
       </spirit:parameters>
     </spirit:busInterface>
   </spirit:busInterfaces>
@@ -333,7 +337,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>abaee39b</spirit:value>
+            <spirit:value>923e7b90</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -849,23 +853,23 @@
       <xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
       <xilinx:definitionSource>package_project</xilinx:definitionSource>
       <xilinx:vendorDisplayName>AMD</xilinx:vendorDisplayName>
-      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:coreRevision>2</xilinx:coreRevision>
       <xilinx:upgrades>
         <xilinx:canUpgradeFrom>user.org:user:memstream_axi_wrapper:1.0</xilinx:canUpgradeFrom>
       </xilinx:upgrades>
-      <xilinx:coreCreationDateTime>2023-05-05T12:43:17Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2023-05-09T10:21:56Z</xilinx:coreCreationDateTime>
       <xilinx:tags>
         <xilinx:tag xilinx:name="nopcore"/>
       </xilinx:tags>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
       <xilinx:xilinxVersion>2022.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="b291ce72"/>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="733f6ab8"/>
       <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="b683eac1"/>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5ac9af6a"/>
-      <xilinx:checksum xilinx:scope="ports" xilinx:value="5d9e07fa"/>
-      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="6a827ccf"/>
-      <xilinx:checksum xilinx:scope="parameters" xilinx:value="a00bfd07"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="3364bcf8"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="8c876e99"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="6488ba6f"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="10eb550f"/>
       <xilinx:targetDRCs>
         <xilinx:targetDRC xilinx:tool="ipi">
           <xilinx:targetDRCOption xilinx:name="ignore_freq_hz" xilinx:value="true"/>

finn-rtllib/memstream/gui/memstream_v1_0.gtcl

 # This file is automatically written.  Do not modify.
-proc gen_USERPARAMETER_AXILITE_ADDR_WIDTH_VALUE {DEPTH WIDTH } {expr 2 + log($DEPTH*pow(2, log(($WIDTH+31)/32)/log(2)))/log(2)}
+proc gen_USERPARAMETER_AXILITE_ADDR_WIDTH_VALUE {DEPTH WIDTH } {expr 2 + ceil(log($DEPTH*pow(2, ceil(log(($WIDTH+31)/32)/log(2))))/log(2))}