Prepare for memstream instantiation as an IP core.

finn-rtllib/memstream/hdl/memstream_axi.sv

@@ -130,7 +130,7 @@ module memstream_axi #(
 		.odat(m_axis_0_tdata[WIDTH-1:0])
 	);
 	if($bits(m_axis_0_tdata) > WIDTH) begin
-		assign	m_axis_0_tdata[$left(m_axis_0_tdata):WIDTH] <= '0;
+		assign	m_axis_0_tdata[$left(m_axis_0_tdata):WIDTH] = '0;
 	end
 
 endmodule : memstream_axi

finn-rtllib/memstream/hdl/memstream_axi_wrapper.v

@@ -31,13 +31,13 @@
  */
 
 module memstream_axi_wrapper #(
-	parameter  DEPTH = $DEPTH$,
-	parameter  WIDTH = $WIDTH$,
+	parameter  DEPTH = 512,
+	parameter  WIDTH = 32,
 
-	parameter  INIT_FILE = $INIT_FILE$,
-	parameter  RAM_STYLE = $RAM_STYLE$,
+	parameter  INIT_FILE = "",
+	parameter  RAM_STYLE = "auto",
 
-	localparam  AXILITE_ADDR_WIDTH = $clog2(DEPTH * (2**$clog2((WIDTH+31)/32))) + 2
+	parameter  AXILITE_ADDR_WIDTH = $clog2(DEPTH * (2**$clog2((WIDTH+31)/32))) + 2
 )(
 	// Global Control
 	(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF m_axis_0" *)
@@ -77,9 +77,15 @@ module memstream_axi_wrapper #(
 	output	[((WIDTH+7)/8)*8-1:0]  m_axis_0_tdata
 );
 
+	localparam  INIT_FILTERED =
+`ifdef SYNTHESIS
+		RAM_STYLE == "ultra"? "" :
+`endif
+		INIT_FILE;
+
 	memstream_axi #(
 		.DEPTH(DEPTH), .WIDTH(WIDTH),
-		.INIT_FILE(INIT_FILE),
+		.INIT_FILE(INIT_FILTERED),
 		.RAM_STYLE(RAM_STYLE)
 	) core (
 		.clk(ap_clk), .rst(!ap_rst_n),

finn-rtllib/memstream/xgui/memstream_v1_0.tcl

+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "DEPTH" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "INIT_FILE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "RAM_STYLE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "WIDTH" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.DEPTH { PARAM_VALUE.DEPTH } {
+	# Procedure called to update DEPTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DEPTH { PARAM_VALUE.DEPTH } {
+	# Procedure called to validate DEPTH
+	return true
+}
+
+proc update_PARAM_VALUE.INIT_FILE { PARAM_VALUE.INIT_FILE } {
+	# Procedure called to update INIT_FILE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.INIT_FILE { PARAM_VALUE.INIT_FILE } {
+	# Procedure called to validate INIT_FILE
+	return true
+}
+
+proc update_PARAM_VALUE.RAM_STYLE { PARAM_VALUE.RAM_STYLE } {
+	# Procedure called to update RAM_STYLE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.RAM_STYLE { PARAM_VALUE.RAM_STYLE } {
+	# Procedure called to validate RAM_STYLE
+	return true
+}
+
+proc update_PARAM_VALUE.WIDTH { PARAM_VALUE.WIDTH } {
+	# Procedure called to update WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.WIDTH { PARAM_VALUE.WIDTH } {
+	# Procedure called to validate WIDTH
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.DEPTH { MODELPARAM_VALUE.DEPTH PARAM_VALUE.DEPTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DEPTH}] ${MODELPARAM_VALUE.DEPTH}
+}
+
+proc update_MODELPARAM_VALUE.WIDTH { MODELPARAM_VALUE.WIDTH PARAM_VALUE.WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.WIDTH}] ${MODELPARAM_VALUE.WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.INIT_FILE { MODELPARAM_VALUE.INIT_FILE PARAM_VALUE.INIT_FILE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.INIT_FILE}] ${MODELPARAM_VALUE.INIT_FILE}
+}
+
+proc update_MODELPARAM_VALUE.RAM_STYLE { MODELPARAM_VALUE.RAM_STYLE PARAM_VALUE.RAM_STYLE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.RAM_STYLE}] ${MODELPARAM_VALUE.RAM_STYLE}
+}
+
+proc update_MODELPARAM_VALUE.AXILITE_ADDR_WIDTH { MODELPARAM_VALUE.AXILITE_ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	# WARNING: There is no corresponding user parameter named "AXILITE_ADDR_WIDTH". Setting updated value from the model parameter.
+set_property value 11 ${MODELPARAM_VALUE.AXILITE_ADDR_WIDTH}
+}
+

src/finn/custom_op/fpgadataflow/matrixvectoractivation.py

@@ -867,29 +867,9 @@ class MatrixVectorActivation(HLSCustomOp):
             self.make_weight_file(weights, "decoupled_npy", weight_filename_sim)
             if mem_mode == "decoupled":
                 # also save weights as Verilog .dat file
-                # note that we provide two different .dat files, one for synth
-                # and one for synthesis. this is because URAM-based weights always
-                # need zero weights for synthesis, otherwise they get inferred
-                # as BRAM
-                weight_filename_rtl_synth = "{}/memblock_synth_0.dat".format(
-                    code_gen_dir
-                )
-                weight_filename_rtl_sim = "{}/memblock_sim_0.dat".format(code_gen_dir)
-                # sim weights are always the true weights
-                self.make_weight_file(
-                    weights, "decoupled_verilog_dat", weight_filename_rtl_sim
-                )
-                ram_style = self.get_nodeattr("ram_style")
-                if ram_style == "ultra":
-                    # UltraRAM must have no memory initializer, or only zeroes
-                    # otherwise BRAM will be inferred instead of URAM
-                    # as a workaround we provide a zero-weight init here
-                    synth_weights = np.zeros_like(weights, dtype=np.float32)
-                else:
-                    synth_weights = weights
-                self.make_weight_file(
-                    synth_weights, "decoupled_verilog_dat", weight_filename_rtl_synth
-                )
+                # This file will be ignored when synthesizing UltraScale memory.
+                weight_filename_rtl = "{}/memblock.dat".format(code_gen_dir)
+                self.make_weight_file(weights, "decoupled_verilog_dat", weight_filename_rtl)
         else:
             raise Exception(
                 """Please set mem_mode to "const", "decoupled", or "external",
@@ -1387,24 +1367,18 @@ class MatrixVectorActivation(HLSCustomOp):
             )
             cmd.append(
                 "set_property -dict [list "
-                "CONFIG.NSTREAMS {1} "
-                "CONFIG.MEM_DEPTH {%d} "
-                "CONFIG.MEM_WIDTH {%d} "
-                "CONFIG.MEM_INIT {%s} "
+                "CONFIG.DEPTH {%d} "
+                "CONFIG.WIDTH {%d} "
+                "CONFIG.INIT_FILE {%s} "
                 "CONFIG.RAM_STYLE {%s} "
-                "CONFIG.STRM0_DEPTH {%d} "
-                "CONFIG.STRM0_WIDTH {%d} "
-                "CONFIG.STRM0_OFFSET {0} "
                 "] [get_bd_cells /%s/%s]"
                 % (
                     self.calc_wmem(),
                     self.get_weightstream_width_padded(),
-                    self.get_nodeattr("code_gen_dir_ipgen") + "/",
+                    self.get_nodeattr("code_gen_dir_ipgen") + "/memblock.dat",
                     self.get_nodeattr("ram_style"),
-                    self.calc_wmem(),
-                    self.get_weightstream_width_padded(),
                     node_name,
-                    strm_inst,
+                    strm_inst
                 )
             )
             cmd.append(