[Test] Change input argument to clock period for make_pynq_proj and create_stitched_ip  transformation

[Transformation and Test] Add option to adjust clock frequency in ipstitch and when making the pynq project get fclk from the metadata properties. Change tfc w1a1 test to test new feature

thanks to @quetric for pointing this out

this will be replaced by a metadata_prop in the near future

slight difference from others: needs ReplaceVerilogRelPaths