[Test] Update other tests that use CreateStitchedIP transformation to use clock period as argument

tests/end2end/test_end2end_cnv_w1a1.py

@@ -178,7 +178,7 @@ def test_end2end_cnv_w1a1_gen_hls_ip():
 def test_end2end_cnv_w1a1_ip_stitch():
     model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_ipgen.onnx")
     model = model.transform(ReplaceVerilogRelPaths())
-    model = model.transform(CreateStitchedIP(test_fpga_part))
+    model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))
     model.save(build_dir + "/end2end_cnv_w1a1_ipstitch.onnx")
 
 

tests/end2end/test_end2end_tfc_w1a2.py

@@ -156,7 +156,7 @@ def test_end2end_tfc_w1a2_gen_hls_ip():
 def test_end2end_tfc_w1a2_ip_stitch():
     model = ModelWrapper(build_dir + "/end2end_tfc_w1a2_ipgen.onnx")
     model = model.transform(ReplaceVerilogRelPaths())
-    model = model.transform(CreateStitchedIP(test_fpga_part))
+    model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))
     model.save(build_dir + "/end2end_tfc_w1a2_ipstitch.onnx")
 
 

tests/end2end/test_end2end_tfc_w2a2.py

@@ -156,7 +156,7 @@ def test_end2end_tfc_w2a2_gen_hls_ip():
 def test_end2end_tfc_w2a2_ip_stitch():
     model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_ipgen.onnx")
     model = model.transform(ReplaceVerilogRelPaths())
-    model = model.transform(CreateStitchedIP(test_fpga_part))
+    model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))
     model.save(build_dir + "/end2end_tfc_w2a2_ipstitch.onnx")
 
 

tests/fpgadataflow/test_fpgadataflow_fifo.py

@@ -98,7 +98,7 @@ def test_fpgadataflow_fifo_rtlsim(Shape, folded_shape, depth, finn_dtype):
     assert y.shape == tuple(Shape), """The output shape is incorrect."""
 
     model = model.transform(ReplaceVerilogRelPaths())
-    model = model.transform(CreateStitchedIP(test_fpga_part))
+    model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))
     model = model.transform(MakePYNQProject(test_pynq_board))
     model = model.transform(SynthPYNQProject())
     model = model.transform(MakePYNQDriver())

tests/fpgadataflow/test_fpgadataflow_ip_stitch.py

@@ -220,7 +220,7 @@ def test_fpgadataflow_ipstitch_do_stitch():
         ip_stitch_model_dir + "/test_fpgadataflow_ipstitch_gen_model.onnx"
     )
     model = model.transform(rvp.ReplaceVerilogRelPaths())
-    model = model.transform(CreateStitchedIP(test_fpga_part))
+    model = model.transform(CreateStitchedIP(test_fpga_part, 5))
     vivado_stitch_proj_dir = model.get_metadata_prop("vivado_stitch_proj")
     assert vivado_stitch_proj_dir is not None
     assert os.path.isdir(vivado_stitch_proj_dir)