[Test] Change input argument to clock period for make_pynq_proj and...

[Test] Change input argument to clock period for make_pynq_proj and create_stitched_ip  transformation

tests/end2end/test_end2end_tfc_w1a1_throughput_test.py

@@ -164,8 +164,7 @@ def test_end2end_tfc_w1a1_gen_hls_ip():
 def test_end2end_tfc_w1a1_ip_stitch():
     model = ModelWrapper(build_dir + "/end2end_tfc_w1a1_ipgen.onnx")
     model = model.transform(ReplaceVerilogRelPaths())
-    fclk_MHz = 1 / (target_clk_ns * 0.001)
-    model = model.transform(CreateStitchedIP(test_fpga_part, fclk_MHz))
+    model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))
     model.save(build_dir + "/end2end_tfc_w1a1_ipstitch.onnx")