From 6c9f31f01d0a26c68e4d0b9be41b5e34fc5fa647 Mon Sep 17 00:00:00 2001
From: auphelia <jakobapk@web.de>
Date: Tue, 12 May 2020 11:07:11 +0100
Subject: [PATCH] [Test] Change input argument to clock period for
make_pynq_proj and create_stitched_ip transformation
---
tests/end2end/test_end2end_tfc_w1a1_throughput_test.py | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py b/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
index 6303990a1..53b82bbd8 100644
--- a/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
+++ b/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
@@ -164,8 +164,7 @@ def test_end2end_tfc_w1a1_gen_hls_ip():
def test_end2end_tfc_w1a1_ip_stitch():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a1_ipgen.onnx")
model = model.transform(ReplaceVerilogRelPaths())
- fclk_MHz = 1 / (target_clk_ns * 0.001)
- model = model.transform(CreateStitchedIP(test_fpga_part, fclk_MHz))
+ model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))
model.save(build_dir + "/end2end_tfc_w1a1_ipstitch.onnx")
--
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