diff --git a/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py b/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
index 6303990a1b7f208acac6c3d9e24acf78ab157d00..53b82bbd8543a84e17b6b623103b62cd4afd115b 100644
--- a/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
+++ b/tests/end2end/test_end2end_tfc_w1a1_throughput_test.py
@@ -164,8 +164,7 @@ def test_end2end_tfc_w1a1_gen_hls_ip():
 def test_end2end_tfc_w1a1_ip_stitch():
     model = ModelWrapper(build_dir + "/end2end_tfc_w1a1_ipgen.onnx")
     model = model.transform(ReplaceVerilogRelPaths())
-    fclk_MHz = 1 / (target_clk_ns * 0.001)
-    model = model.transform(CreateStitchedIP(test_fpga_part, fclk_MHz))
+    model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))
     model.save(build_dir + "/end2end_tfc_w1a1_ipstitch.onnx")