Commits · c4256c3c1f83fc43d29cd2bd502cf386d5f8146c · streichg / Finn · GitLab

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Jan 31, 2023
- [FMPadding] Increase counter bits for rtl component · c4256c3c
  auphelia authored 2 years ago
  
  c4256c3c
Jan 26, 2023
- [Transform] Add defaults, docstring and comments to split large fifos · dcf82a0c
  auphelia authored 2 years ago
  
  dcf82a0c
- [pyverilator] Add arguments to cpp verilator simulation · c60d955b
  auphelia authored 2 years ago
  
  c60d955b
Jan 18, 2023
- [Docs] Fix docstring in SplitLargeFIFOs transform · 2008d154
  auphelia authored 2 years ago
  
  2008d154
Jan 17, 2023
- [CustomOp] Update ImgDim and numReps in thresholding · 64306ba7
  auphelia authored 2 years ago
  
  64306ba7
- [MVAU] Update minimize accumulator width for bipolar case · 4d5e0458
  auphelia authored 2 years ago
  
  4d5e0458
Jan 11, 2023
- [QONNX] make valid_predecessor_op_type a method, fallback to QuantIdentityHandler · 54283158
  Yaman Umuroglu authored 2 years ago
  
  54283158
Jan 10, 2023
- [Util] Change np.int to np.int_ · 5ad48be5
  auphelia authored 2 years ago
  
  5ad48be5
Jan 09, 2023
- [DataPacking] Delete check for np.str · 1b8bf757
  auphelia authored 2 years ago
  
  1b8bf757
Jan 05, 2023
- [CustomOp] Fix setting of NumReps in Thresholding and N in Eltwise node · 99a91584
  auphelia authored 2 years ago
  
  99a91584
Dec 30, 2022
- [Docs] Fix docstrings in modules · fe6dca92
  auphelia authored 2 years ago
  
  fe6dca92
Dec 19, 2022
- [HLSCustomOp] single-source + prep util fxns for node-by-node rtlsim · e809dab5
  Yaman Umuroglu authored 2 years ago
  
  e809dab5
- [Util] refactor verilator prep into two functions · 2c5d07fa
  Yaman Umuroglu authored 2 years ago
  
  2c5d07fa
Dec 13, 2022
- [Util] remove redundant code from pyverilator utils · fd9a8541
  Yaman Umuroglu authored 2 years ago
  
  fd9a8541
Dec 08, 2022
- [VitisBuild] Reverse check for node name in ipgen and add prefix for node names in vitis build · 5bfdc0e0
  auphelia authored 2 years ago
  
  5bfdc0e0
Dec 02, 2022
- [FIFO] cleaner impl of get_fifo_split_configs · f5b8a2e8
  Yaman Umuroglu authored 2 years ago
  
  f5b8a2e8
- [FIFO] better documentation for SplitLargeFIFOs, FIFO in caps · 5d954037
  Yaman Umuroglu authored 2 years ago
  
  5d954037
- [Build] move FIFO splitting past final json folding config file gen · bce67e95
  Yaman Umuroglu authored 2 years ago
  
  bce67e95
- [FIFO] support FIFO splitting for pow2 size optimizations · a5ffaca3
  Yaman Umuroglu authored 2 years ago
  
  a5ffaca3
Nov 16, 2022
- [fix-comments]: in/outFIFODepth renamed to in/outFIFODepths · ea7518e2
  mmrahorovic authored 2 years ago
  
  ea7518e2
Nov 13, 2022

[FIFO] bugfixes+improvements in verilator fifosim template · c8b5368d

Yaman Umuroglu authored 2 years ago

- move input token counting to after clock tick
- introduce separate tracker for last seen output
- introduce (disabled by default) vcd tracing capabilities

c8b5368d

Nov 10, 2022
- [FIFO] improve C++ FIFO sizing template · 8fe057cc
  Yaman Umuroglu authored 2 years ago
  
  8fe057cc
- [FIFO] also generate compilation script for C++ FIFO sizing · 9f8cf74b
  Yaman Umuroglu authored 2 years ago
  
  9f8cf74b
Nov 01, 2022
- [Streamline/Absorb] Reorder insertion/rewire of new trn node · c3083929
  auphelia authored 2 years ago
  
  c3083929
- [Convert] skip streaming eltwise conversion if static inputs · a8343b2d
  Yaman Umuroglu authored 2 years ago
  
  a8343b2d
Oct 27, 2022
- [CustomOp] Add dtype functions to StreamingFIFO · ad6319d5
  auphelia authored 2 years ago
  
  ad6319d5
Oct 26, 2022
- [set_fifo_depths] Adding a new transformation to split fifos larger than the max allowed depth · 1c7d81f3
  Hugo LE BLEVEC authored 2 years ago
  
  1c7d81f3
Oct 24, 2022
- [CustomOp] Delete stream depth pragmas for in/out streams in MVAU and VVAUs · 5d8a0260
  auphelia authored 2 years ago
  
  5d8a0260
- [SWGG] incorporate Yaman's changes + small fixes · 83550c64
  Felix Jentzsch authored 2 years ago
  
  83550c64
Oct 21, 2022
- [Transform] Extend inFIFODepths for extw nodes · c7c15b7c
  auphelia authored 2 years ago
  
  c7c15b7c
- [SWG] generate wren as part of config reg generation · a2de7013
  Yaman Umuroglu authored 2 years ago
  
  a2de7013
- [Pad] use contiguous, 4b-aligned config addrs for RTL variant · 79d64148
  Yaman Umuroglu authored 2 years ago
  
  79d64148
- [DynConv] make get_dynamic_config return defaults with None params · 46257f31
  Yaman Umuroglu authored 2 years ago
  
  46257f31
- [SWGG] rename dynamic cfg interface to s_axilite · 6e91fcd6
  Yaman Umuroglu authored 2 years ago
  
  6e91fcd6
Oct 17, 2022
- [Pad] bring FMPadding_rtl shape/dtype/stream fxn interfaces up to speed · 0bfcc545
  Yaman Umuroglu authored 2 years ago
  
  0bfcc545
Oct 16, 2022
- [Pad] bugfix: use dynamic parameters for dynamic config gen · 1bfb12f1
  Yaman Umuroglu authored 2 years ago
  
  1bfb12f1
- [Pad] switch top-level template SystemVerilog->Verilog · cb0bf3cb
  Yaman Umuroglu authored 2 years ago
  
  this keeps Vivado happy for interface inference for blocks
  cb0bf3cb
Oct 14, 2022
- [Pad] bugfixes in FMPadding_rtl config gen · 9d4f4ae0
  Yaman Umuroglu authored 2 years ago
  
  9d4f4ae0
Oct 13, 2022
- [Pad] add FMPadding_rtl to op registry, fixes to its CustomOp · d6feac78
  Yaman Umuroglu authored 2 years ago
  
  d6feac78
Oct 12, 2022
- [FMPadding] conversion, inst template, CustomOp for FMPadding_rtl · 4f4bec7a
  Yaman Umuroglu authored 2 years ago
  
  4f4bec7a