[SWG] generate wren as part of config reg generation

src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py

@@ -885,6 +885,7 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp):
         # each setting is mapped to an axi-lite register address
         template_path, code_gen_dict = self.prepare_codegen_default()
         config = {
+            "cfg_wren": (0 * 4, 1),
             "cfg_cntr_simd": (1 * 4, int(code_gen_dict["$LOOP_SIMD_ITERATIONS$"][0])),
             "cfg_cntr_kw": (2 * 4, int(code_gen_dict["$LOOP_KW_ITERATIONS$"][0])),
             "cfg_cntr_kh": (3 * 4, int(code_gen_dict["$LOOP_KH_ITERATIONS$"][0])),

tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py

@@ -151,14 +151,10 @@ def config_hook(configs):
 
     def write_swg_config(sim):
         for axi_name, config in configs:
-            # 1. Write config registers to the SWG, dict defines (addr, value) tuples
+            # Write config registers to the SWG/FMPadding dict
+            # defines (addr, value) tuples
             for config_entry in config.values():
                 axilite_write(sim, config_entry[0], config_entry[1], basename=axi_name)
-            # 2. Set cfg_valid flag (>= 1 cycle) for SWGG
-            # TODO direct add wren register to generated config?
-            if len(config) == 15:
-                axilite_write(sim, 0, 1, basename=axi_name)
-        # 3. Reset component (>= 1 cycle)
         reset_rtlsim(sim)
 
     return write_swg_config