Commits · 8e84036e468d3abd0f08d8c84d353c16062c1a0e · streichg / Finn · GitLab

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Oct 27, 2022
- [SWGG] improve HDL code · 3d002f7e
  Felix Jentzsch authored 2 years ago
  
  3d002f7e
Oct 24, 2022
- [SWGG] incorporate Yaman's changes + small fixes · 83550c64
  Felix Jentzsch authored 2 years ago
  
  83550c64
Oct 21, 2022
- [Pad] use contiguous, 4b-aligned config addrs for RTL variant · 79d64148
  Yaman Umuroglu authored 2 years ago
  
  79d64148
- [SWGG] rename dynamic cfg interface to s_axilite · 6e91fcd6
  Yaman Umuroglu authored 2 years ago
  
  6e91fcd6
Oct 17, 2022
- [Pad] typo fix in template · 835ba0fa
  Yaman Umuroglu authored 2 years ago
  
  835ba0fa
- [Pad] more changes to RTL inst template for Verilog compatibility · 43a37155
  Yaman Umuroglu authored 2 years ago
  
  43a37155
Oct 16, 2022
- [Pad] switch top-level template SystemVerilog->Verilog · cb0bf3cb
  Yaman Umuroglu authored 2 years ago
  
  this keeps Vivado happy for interface inference for blocks
  cb0bf3cb
Oct 14, 2022
- Add sanity checking for generics. · ff348d47
  Thomas B. Preußer authored 2 years ago
  
  ff348d47
Oct 13, 2022
- [Pad] update fmpadding_rtl template · e2cc28d3
  Yaman Umuroglu authored 2 years ago
  
  e2cc28d3
- Added capability to custom-initialize dynamic parameter registers upon design configuration. · ba9a45f0
  Thomas B. Preußer authored 2 years ago
  
  ba9a45f0
Oct 12, 2022
- [FMPadding] conversion, inst template, CustomOp for FMPadding_rtl · 4f4bec7a
  Yaman Umuroglu authored 2 years ago
  
  4f4bec7a
- Added AXI-Light adapter to dynamically-sized feature map padding. · ee2748a2
  Thomas B. Preußer authored 2 years ago
  
  ee2748a2
- First prototype for dynamically sized FM padding. · cba8536a
  Thomas B. Preußer authored 2 years ago
  
  cba8536a
Oct 11, 2022
- Added AXI-Light adapter to dynamically-sized feature map padding. · 03ccfb5e
  Thomas B. Preußer authored 2 years ago
  
  03ccfb5e
Oct 10, 2022
- First prototype for dynamically sized FM padding. · c52ab50d
  Thomas B. Preußer authored 2 years ago
  
  c52ab50d
Oct 04, 2022
- FIFO] bugfix post-reset ibp condition on Q_srl · 1a4166c9
  Yaman Umuroglu authored 2 years ago
  
  1a4166c9
Sep 27, 2022
- [FIFO] SystemVerilog -> Verilog fix in Q_srl.v · a8d3fb6c
  Yaman Umuroglu authored 2 years ago
  
  a8d3fb6c
Sep 26, 2022
- [FIFO] SystemVerilog -> Verilog fix in Q_srl.v · dc830f11
  Yaman Umuroglu authored 2 years ago
  
  dc830f11
Sep 22, 2022
- [Style] Minor style fixes to added components · fdb00bb5
  auphelia authored 2 years ago
  
  fdb00bb5
- Working initial implementation · ecb5a7e3
  Felix Jentzsch authored 2 years ago
  
  ecb5a7e3
Sep 19, 2022
- [FIFO] add hw maxcount tracking to rtl FIFOs with opt attribute · e8f7c756
  Yaman Umuroglu authored 2 years ago
  
  e8f7c756
Sep 16, 2022
- Address reviewer comments · 5e0e8989
  Felix Jentzsch authored 2 years ago
  
  5e0e8989
Sep 09, 2022
- Move parallel impl. to different branch, cleanup · 57f9fecd
  Felix Jentzsch authored 2 years ago
  
  57f9fecd
Aug 24, 2022
- Restructure, basic resource estimation · f46e2d0a
  Felix Jentzsch authored 2 years ago
  
  f46e2d0a
Jul 14, 2022
- Revert "Merge pull request #637 from Xilinx/dev" · 963fde53
  auphelia authored 2 years ago
  
  This reverts commit fe4a150c, reversing changes made to c98c2211.
  963fde53
Jul 12, 2022
- Fixes for tests, ooc synth, clocking · 7fd6a640
  Felix Jentzsch authored 2 years ago
  
  7fd6a640
Jul 05, 2022
- Adapt to upcoming FINN release · 53ffa343
  Felix Jentzsch authored 2 years ago
  
  53ffa343
- Improve Systemverilog, extend tests · 3a2a8508
  Felix Jentzsch authored 2 years ago
  
  3a2a8508
Jun 29, 2022
- [Refactor] Change copyright header · 7750fbb0
  auphelia authored 2 years ago
  
  7750fbb0
Jun 28, 2022
- [Pre-commit] pre-commit fixes of axi-info tcl script and Jenkinsfile · fa2401a8
  auphelia authored 2 years ago
  
  fa2401a8
Jun 17, 2022
- Hotfix: Instance name for axi_info instantiation. · 889ba2ce
  Thomas B. Preußer authored 2 years ago
  
  889ba2ce
- Hotfix: Instance name for axi_info instantiation. · dd704a6c
  Thomas B. Preußer authored 2 years ago
  
  dd704a6c
Jun 13, 2022
- Cleanup and fixes · 34f82112
  Felix Jentzsch authored 2 years ago
  
  34f82112
Jun 12, 2022
- Add conventional implementation style for out_width <= in_width · 0ae77fe7
  Felix Jentzsch authored 2 years ago
  
  0ae77fe7
May 31, 2022
- [finn-rtllib] Update ip for axi-info · 989fbdae
  auphelia authored 2 years ago
  
  989fbdae
May 30, 2022
- Fixed signature composition. · e88a0295
  Thomas B. Preußer authored 2 years ago
  
  e88a0295
May 25, 2022
- [finn rtllib] Add updated packaged ip for axi_info · d47a5599
  auphelia authored 2 years ago
  
  d47a5599
- axi_info read not to block upon out-of-bounds accesses. · 5d0da833
  Thomas B. Preußer authored 2 years ago
  
  5d0da833
May 24, 2022
- [Refactor] move checksum files to under custom_hls · dac25880
  Yaman Umuroglu authored 2 years ago
  
  dac25880
May 23, 2022
- Packaged IP infrastructure for axi_info. · f7173c99
  Thomas B. Preußer authored 2 years ago
  
  f7173c99