Commits · 96fc4f57670811fafe1753a63bf0ccfc521da077 · streichg / Finn

Jun 23, 2023
- Trying a package for replacing the global ifdef'ed declaration. · 175e7c60
  Thomas B. Preußer authored 1 year ago
  
  175e7c60
Mar 23, 2023
- [SWG] Incorporate minor comments on Verilog code · 24bd1907
  Felix Jentzsch authored 2 years ago
  
  24bd1907
Mar 14, 2023
- [SWG] Move common modules to static source file · 40eb5c7d
  Felix Jentzsch authored 2 years ago
  
  40eb5c7d
Jan 27, 2023
- [SWG] Adjust resource estimates, set_folding · 7f4b20f6
  Felix Jentzsch authored 2 years ago
  
  7f4b20f6
Dec 01, 2022
- [RTL SWG] Rework parallel-output implementation style · 0fb57af5
  Felix Jentzsch authored 2 years ago
  
  0fb57af5
Oct 27, 2022
- [SWGG] improve HDL code · 3d002f7e
  Felix Jentzsch authored 2 years ago
  
  3d002f7e
Oct 24, 2022
- [SWGG] incorporate Yaman's changes + small fixes · 83550c64
  Felix Jentzsch authored 2 years ago
  
  83550c64
Sep 22, 2022
- [Style] Minor style fixes to added components · fdb00bb5
  auphelia authored 2 years ago
  
  fdb00bb5
- Working initial implementation · ecb5a7e3
  Felix Jentzsch authored 2 years ago
  
  ecb5a7e3
Sep 16, 2022
- Address reviewer comments · 5e0e8989
  Felix Jentzsch authored 2 years ago
  
  5e0e8989
Sep 09, 2022
- Move parallel impl. to different branch, cleanup · 57f9fecd
  Felix Jentzsch authored 2 years ago
  
  57f9fecd
Jul 05, 2022
- Improve Systemverilog, extend tests · 3a2a8508
  Felix Jentzsch authored 2 years ago
  
  3a2a8508
Jun 13, 2022
- Cleanup and fixes · 34f82112
  Felix Jentzsch authored 2 years ago
  
  34f82112
Jun 12, 2022
- Add conventional implementation style for out_width <= in_width · 0ae77fe7
  Felix Jentzsch authored 2 years ago
  
  0ae77fe7

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