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Commit 175e7c60 authored by Thomas B. Preußer's avatar Thomas B. Preußer
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Trying a package for replacing the global ifdef'ed declaration.

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/******************************************************************************
* Copyright (C) 2022, Advanced Micro Devices, Inc.
* Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
......@@ -29,20 +29,10 @@
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
`ifndef FINN_SWG_ENUM_DEFINED
`define FINN_SWG_ENUM_DEFINED
typedef enum logic [2:0] {
STATE_START,
STATE_LOOP_SIMD,
STATE_LOOP_KW,
STATE_LOOP_KH,
STATE_LOOP_W,
STATE_LOOP_H
} state_e;
`endif
// loop controller used for both, "default" and "parallel", implementation styles
module swg_controller #(
module swg_controller
import swg::*; #(
int unsigned LOOP_H_ITERATIONS,
int unsigned LOOP_W_ITERATIONS,
int unsigned LOOP_KH_ITERATIONS,
......@@ -62,7 +52,7 @@ module swg_controller #(
int TAIL_INCR_H,
int TAIL_INCR_LAST,
parameter INNERMOST_STATE
state_e INNERMOST_STATE
)(
input logic clk,
input logic rst_n,
......
/******************************************************************************
* Copyright (C) 2023, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
package swg;
typedef enum logic [2:0] {
STATE_START,
STATE_LOOP_SIMD,
STATE_LOOP_KW,
STATE_LOOP_KH,
STATE_LOOP_W,
STATE_LOOP_H
} state_e;
endpackage : swg
/******************************************************************************
* Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
`timescale 1 ns / 1 ps
module $TOP_MODULE_NAME$_axilite #
(
module $TOP_MODULE_NAME$_axilite #(
// Users to add parameters here
// User parameters ends
......@@ -12,8 +39,7 @@ module $TOP_MODULE_NAME$_axilite #
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 6
)
(
)(
// Users to add ports here
output wire [C_S_AXI_DATA_WIDTH-1:0] cfg_reg0,
output wire [C_S_AXI_DATA_WIDTH-1:0] cfg_reg1,
......
......@@ -98,7 +98,7 @@ module $TOP_MODULE_NAME$_impl #(
.TAIL_INCR_LAST($TAIL_INCR_LAST$),
.INCR_BITWIDTH($INCR_BITWIDTH$),
.IS_DEPTHWISE($IS_DEPTHWISE$),
.INNERMOST_STATE($INNERMOST_STATE$)
.INNERMOST_STATE(swg::$INNERMOST_STATE$)
)
controller_inst (
.clk(ap_clk),
......
`ifndef FINN_SWG_ENUM_DEFINED
`define FINN_SWG_ENUM_DEFINED
typedef enum logic [2:0] {
STATE_START,
STATE_LOOP_SIMD,
STATE_LOOP_KW,
STATE_LOOP_KH,
STATE_LOOP_W,
STATE_LOOP_H
} state_e;
`endif
/******************************************************************************
* Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
module $TOP_MODULE_NAME$_controller #(
int unsigned CNTR_BITWIDTH,
......@@ -39,6 +58,8 @@ module $TOP_MODULE_NAME$_controller #(
input logic [INCR_BITWIDTH-1:0] cfg_incr_tail_last
);
import swg::*;
// (dynamic) configuration registers
logic [CNTR_BITWIDTH-1:0] Cfg_cntr_simd = $LOOP_SIMD_ITERATIONS$;
logic [CNTR_BITWIDTH-1:0] Cfg_cntr_kw = $LOOP_KW_ITERATIONS$;
......
......@@ -123,7 +123,7 @@ module $TOP_MODULE_NAME$_impl #(
.TAIL_INCR_LAST($TAIL_INCR_LAST$),
.INCR_BITWIDTH($INCR_BITWIDTH$),
.IS_DEPTHWISE($IS_DEPTHWISE$),
.INNERMOST_STATE($INNERMOST_STATE$)
.INNERMOST_STATE(swg::$INNERMOST_STATE$)
)
controller_inst (
.clk(ap_clk),
......
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