diff --git a/finn-rtllib/swg/swg_common.sv b/finn-rtllib/swg/swg_common.sv
index d953078abedd1beddccb1314c712c29a57db995d..f2cdc333cad0a546aa9cfb55c9ca1dd74a753dc2 100644
--- a/finn-rtllib/swg/swg_common.sv
+++ b/finn-rtllib/swg/swg_common.sv
@@ -1,5 +1,5 @@
/******************************************************************************
- * Copyright (C) 2022, Advanced Micro Devices, Inc.
+ * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -29,20 +29,10 @@
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
-`ifndef FINN_SWG_ENUM_DEFINED
-`define FINN_SWG_ENUM_DEFINED
-typedef enum logic [2:0] {
- STATE_START,
- STATE_LOOP_SIMD,
- STATE_LOOP_KW,
- STATE_LOOP_KH,
- STATE_LOOP_W,
- STATE_LOOP_H
-} state_e;
-`endif
// loop controller used for both, "default" and "parallel", implementation styles
-module swg_controller #(
+module swg_controller
+import swg::*; #(
int unsigned LOOP_H_ITERATIONS,
int unsigned LOOP_W_ITERATIONS,
int unsigned LOOP_KH_ITERATIONS,
@@ -62,7 +52,7 @@ module swg_controller #(
int TAIL_INCR_H,
int TAIL_INCR_LAST,
- parameter INNERMOST_STATE
+ state_e INNERMOST_STATE
)(
input logic clk,
input logic rst_n,
diff --git a/finn-rtllib/swg/swg_pkg.sv b/finn-rtllib/swg/swg_pkg.sv
new file mode 100644
index 0000000000000000000000000000000000000000..1200310acad2931568235a82fd0277b8dd50a424
--- /dev/null
+++ b/finn-rtllib/swg/swg_pkg.sv
@@ -0,0 +1,41 @@
+/******************************************************************************
+ * Copyright (C) 2023, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
+
+package swg;
+ typedef enum logic [2:0] {
+ STATE_START,
+ STATE_LOOP_SIMD,
+ STATE_LOOP_KW,
+ STATE_LOOP_KH,
+ STATE_LOOP_W,
+ STATE_LOOP_H
+ } state_e;
+endpackage : swg
diff --git a/finn-rtllib/swg/swg_template_axilite.v b/finn-rtllib/swg/swg_template_axilite.v
index 9479c7f80d7d82b27141dbe5abcce442049237bd..1f39e4440e47f752816907dc454d15b849c8fa85 100644
--- a/finn-rtllib/swg/swg_template_axilite.v
+++ b/finn-rtllib/swg/swg_template_axilite.v
@@ -1,8 +1,35 @@
+/******************************************************************************
+ * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
-`timescale 1 ns / 1 ps
-
-module $TOP_MODULE_NAME$_axilite #
-(
+module $TOP_MODULE_NAME$_axilite #(
// Users to add parameters here
// User parameters ends
@@ -12,8 +39,7 @@ module $TOP_MODULE_NAME$_axilite #
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 6
-)
-(
+)(
// Users to add ports here
output wire [C_S_AXI_DATA_WIDTH-1:0] cfg_reg0,
output wire [C_S_AXI_DATA_WIDTH-1:0] cfg_reg1,
diff --git a/finn-rtllib/swg/swg_template_default.sv b/finn-rtllib/swg/swg_template_default.sv
index 4970762172b5bcc1c418c5bbb60bdfee52568dd8..78a8d0a3b984b987df6ca62f3789fbbedcbc6d8b 100644
--- a/finn-rtllib/swg/swg_template_default.sv
+++ b/finn-rtllib/swg/swg_template_default.sv
@@ -98,7 +98,7 @@ module $TOP_MODULE_NAME$_impl #(
.TAIL_INCR_LAST($TAIL_INCR_LAST$),
.INCR_BITWIDTH($INCR_BITWIDTH$),
.IS_DEPTHWISE($IS_DEPTHWISE$),
- .INNERMOST_STATE($INNERMOST_STATE$)
+ .INNERMOST_STATE(swg::$INNERMOST_STATE$)
)
controller_inst (
.clk(ap_clk),
diff --git a/finn-rtllib/swg/swg_template_default_dynamic.sv b/finn-rtllib/swg/swg_template_default_dynamic.sv
index c1647ef6992ea17132decc42b7bc7912f05ae260..5a6fdda170242b804353cac186c1f920a4a71d7a 100644
--- a/finn-rtllib/swg/swg_template_default_dynamic.sv
+++ b/finn-rtllib/swg/swg_template_default_dynamic.sv
@@ -1,14 +1,33 @@
-`ifndef FINN_SWG_ENUM_DEFINED
-`define FINN_SWG_ENUM_DEFINED
-typedef enum logic [2:0] {
- STATE_START,
- STATE_LOOP_SIMD,
- STATE_LOOP_KW,
- STATE_LOOP_KH,
- STATE_LOOP_W,
- STATE_LOOP_H
-} state_e;
-`endif
+/******************************************************************************
+ * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
module $TOP_MODULE_NAME$_controller #(
int unsigned CNTR_BITWIDTH,
@@ -39,6 +58,8 @@ module $TOP_MODULE_NAME$_controller #(
input logic [INCR_BITWIDTH-1:0] cfg_incr_tail_last
);
+ import swg::*;
+
// (dynamic) configuration registers
logic [CNTR_BITWIDTH-1:0] Cfg_cntr_simd = $LOOP_SIMD_ITERATIONS$;
logic [CNTR_BITWIDTH-1:0] Cfg_cntr_kw = $LOOP_KW_ITERATIONS$;
diff --git a/finn-rtllib/swg/swg_template_parallel.sv b/finn-rtllib/swg/swg_template_parallel.sv
index b55a51e4005a1a8332ebe74acb61eac10f246f7f..83a525ff36b883122cd31a59675557a23085a872 100644
--- a/finn-rtllib/swg/swg_template_parallel.sv
+++ b/finn-rtllib/swg/swg_template_parallel.sv
@@ -123,7 +123,7 @@ module $TOP_MODULE_NAME$_impl #(
.TAIL_INCR_LAST($TAIL_INCR_LAST$),
.INCR_BITWIDTH($INCR_BITWIDTH$),
.IS_DEPTHWISE($IS_DEPTHWISE$),
- .INNERMOST_STATE($INNERMOST_STATE$)
+ .INNERMOST_STATE(swg::$INNERMOST_STATE$)
)
controller_inst (
.clk(ap_clk),