Commits · 96fc4f57670811fafe1753a63bf0ccfc521da077 · streichg / Finn · GitLab

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May 24, 2023
- Revised control interface attributes. · 30a0058f
  Thomas B. Preußer authored 1 year ago
  
  30a0058f
May 23, 2023
- Add missing simulation fileset. · e5f4a2c5
  Thomas B. Preußer authored 1 year ago
  
  e5f4a2c5
May 16, 2023
- Polish interface attributes. Use all-lower-case finn library name like other modules. · f15c00d8
  Thomas B. Preußer authored 1 year ago
  
  f15c00d8
May 09, 2023
- Yet another fix of the address width expression for IP integrator. · 0bb289ca
  Thomas B. Preußer authored 1 year ago
  
  0bb289ca
May 05, 2023
- [rtllib] Linting of updated tcl script · 96277dba
  auphelia authored 1 year ago
  
  96277dba
- Have IPI recompute AXI-lite address width according to user-defined memory layout. · 06ab3ecc
  Thomas B. Preußer authored 1 year ago
  
  06ab3ecc
Apr 24, 2023
- [rtllib] linting on tcl script · cd8c6817
  auphelia authored 1 year ago
  
  cd8c6817
Apr 21, 2023
- [finn-rtllib] Re-instantiate FIFO rtl implementation · 763d876e
  auphelia authored 1 year ago
  
  763d876e
- Renaming configuration interface to s_axilite. · c179c0cd
  Thomas B. Preußer authored 1 year ago
  
  c179c0cd
- Prepare for memstream instantiation as an IP core. · 1155ac40
  Thomas B. Preußer authored 1 year ago
  
  1155ac40
Apr 18, 2023
- Adding FINN instantiation template for revised memstream module. · 39e4c313
  Thomas B. Preußer authored 1 year ago
  
  39e4c313
- Streamlined memstream module tested with random interleaved parameter readback. · 9ee018ff
  Thomas B. Preußer authored 1 year ago
  
  9ee018ff
Oct 04, 2022
- FIFO] bugfix post-reset ibp condition on Q_srl · 1a4166c9
  Yaman Umuroglu authored 2 years ago
  
  1a4166c9
Sep 27, 2022
- [FIFO] SystemVerilog -> Verilog fix in Q_srl.v · a8d3fb6c
  Yaman Umuroglu authored 2 years ago
  
  a8d3fb6c
Sep 26, 2022
- [FIFO] SystemVerilog -> Verilog fix in Q_srl.v · dc830f11
  Yaman Umuroglu authored 2 years ago
  
  dc830f11
Sep 19, 2022
- [FIFO] add hw maxcount tracking to rtl FIFOs with opt attribute · e8f7c756
  Yaman Umuroglu authored 2 years ago
  
  e8f7c756
Jul 14, 2022
- Revert "Merge pull request #637 from Xilinx/dev" · 963fde53
  auphelia authored 2 years ago
  
  This reverts commit fe4a150c, reversing changes made to c98c2211.
  963fde53
May 23, 2022
- [HLSCustomOp] generate separate sync/sim .dat files for decoupled · 833be8e1
  Yaman Umuroglu authored 2 years ago
  
  833be8e1
Nov 30, 2021
- [Vitis] minor fixes for 2021.1 and Versal Prime parts · 91eaf3b1
  Yaman Umuroglu authored 3 years ago
  
  91eaf3b1
Sep 30, 2021
- Updated achritecture families to all current types, minus the CPLDs · bda18b3d
  john authored 3 years ago
  
  bda18b3d
Jul 02, 2021
- Converted *.v files from CRLF line endings to LF. · 486a94aa
  Hendrik Borras authored 3 years ago
  
  486a94aa
- Reverted .dat-file change and excluded .dat files trailing-whitespace hook · b9db2e2c
  Hendrik Borras authored 3 years ago
  
  b9db2e2c
Jun 25, 2021
- Applied new pre-commit-config to all files, potentially critical changes only · 51b95ca1
  Hendrik Borras authored 3 years ago
  
  51b95ca1
- Applied new pre-commit-config to all files, non-critical changes only · 3dc48c57
  Hendrik Borras authored 3 years ago
  
  3dc48c57
Dec 17, 2020
- [Release] merge dev into master for v0.5b · 4fee6ffd
  Yaman Umuroglu authored 4 years ago
  
  4fee6ffd
Oct 14, 2020
- [Docs] document flushing requirement after AXI lite read/write · c5c5f214
  Yaman Umuroglu authored 4 years ago
  
  c5c5f214
Oct 12, 2020
- Fixed signal assignment · 6eea8ddf
  Lucian Petrica authored 4 years ago
  
  6eea8ddf
- Fix for MEM_WIDTH==32 · 10dee40a
  Lucian Petrica authored 4 years ago
  
  10dee40a
- Some documentation for the streamer address map · 2df7959b
  Lucian Petrica authored 4 years ago
  
  2df7959b
- Added missing IP file · 735dca29
  Lucian Petrica authored 4 years ago
  
  735dca29
Oct 09, 2020
- Added AXILite interface for writing weights; tested in behavioural sim with 1 stream · ee57c98c
  Lucian Petrica authored 4 years ago
  
  ee57c98c
Sep 24, 2020
- Wired up config interface when depth=1 and nstreams <= 2 · 112c4705
  Lucian Petrica authored 4 years ago
  
  112c4705
Sep 21, 2020
- Implemented FIFO auto-sizing · 5d24f433
  Lucian Petrica authored 4 years ago
  
  5d24f433
Sep 17, 2020
- Added all synthesis source files to be used for simulation too · 27863700
  john authored 4 years ago
  
  27863700
Aug 21, 2020
- Updated streamer core - added RAM_STYLE parameter, implemented with SDP RAM... · f855ee52
  Lucian Petrica authored 4 years ago
  
  Updated streamer core - added RAM_STYLE parameter, implemented with SDP RAM when using just one stream
  f855ee52
Aug 12, 2020
- Implemented explicit solution for DEPTH=1 corner-case · f78176a6
  Lucian Petrica authored 4 years ago
  
  f78176a6
Aug 10, 2020
- Cleaned up core xml, set all support levels to Production · 6c4e55b0
  Lucian Petrica authored 4 years ago
  
  6c4e55b0
- Fixed address range of readmemh in rtl streamer · a1c1e14c
  Lucian Petrica authored 4 years ago
  
  a1c1e14c
Aug 01, 2020
- Modified RTL streamer and its instantiation template, removing need for Q_srl in decoupled mode · 8eda4b18
  Lucian Petrica authored 4 years ago
  
  8eda4b18
Jul 27, 2020
- [rtllib] Update component.xml for virtexuplusHBM devices · 841617c2
  Yaman Umuroglu authored 4 years ago
  
  Unverified
  
  841617c2