Commits · 4c0978e8fb9e845fac6b1b1c32d7b6fa1be4106c · streichg / Finn · GitLab

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Oct 06, 2022
- [CustomOp] Update fmpadding to new hls code · 4c0978e8
  auphelia authored 2 years ago
  
  4c0978e8
Oct 04, 2022
- [Util] Add comment about usage of axis infrastructure vh · 1ce5af77
  auphelia authored 2 years ago
  
  1ce5af77
Sep 26, 2022
- [customOp] Temp. reverse changes to checksum axilite interface name · 584f0fb5
  auphelia authored 2 years ago
  
  584f0fb5
Sep 23, 2022
- [customOp] Fix typo in eltwise customOp · edf0a91e
  auphelia authored 2 years ago
  
  edf0a91e
- [CustomOp] Add comments to convinputgen rtl · 77f07339
  auphelia authored 2 years ago
  
  77f07339
Sep 22, 2022
- [Style] Minor style fixes to added components · fdb00bb5
  auphelia authored 2 years ago
  
  fdb00bb5
Sep 20, 2022
- [InsertDWC] use impl_style=vivado if widths not divisible · d4e91a19
  Yaman Umuroglu authored 2 years ago
  
  d4e91a19
- [FIFO] instead of fixed-depth large FIFO in sim, use tensor size · 6ccc9499
  Yaman Umuroglu authored 2 years ago
  
  6ccc9499
- [FIFO] instead of fixed-depth large FIFO in sim, use tensor size · 20e4613f
  Yaman Umuroglu authored 2 years ago
  
  20e4613f
Sep 19, 2022
- [FIFO] use hw maxcount monitoring in InsertAndSetFIFODepths · 81f010b8
  Yaman Umuroglu authored 2 years ago
  
  81f010b8
- [FIFO] add hw maxcount tracking to rtl FIFOs with opt attribute · e8f7c756
  Yaman Umuroglu authored 2 years ago
  
  e8f7c756
Sep 16, 2022
- Address reviewer comments · 5e0e8989
  Felix Jentzsch authored 2 years ago
  
  5e0e8989
Sep 14, 2022
- [Test] batch-4 inputs and result checking for test_build_dataflow · 10329d79
  Yaman Umuroglu authored 2 years ago
  
  10329d79
- [Build] keep different vcd's from batch inputs · 08134558
  Yaman Umuroglu authored 2 years ago
  
  08134558
- [Util] set property on SDP nodes to get full context · 25499411
  Yaman Umuroglu authored 2 years ago
  
  25499411
- [Build] support batched verification i/o, one at a time · 38d65435
  Yaman Umuroglu authored 2 years ago
  
  38d65435
Sep 09, 2022
- Lint fix · dfb42854
  Felix Jentzsch authored 2 years ago
  
  dfb42854
- Move parallel impl. to different branch, cleanup · 57f9fecd
  Felix Jentzsch authored 2 years ago
  
  57f9fecd
- [pre-commit] Run pre-commit on lookup layer file · 91e3df89
  auphelia authored 2 years ago
  
  91e3df89
- Rebalanced lookup implementation code to go mostly into header file. · 8408b45a
  Thomas B. Preußer authored 2 years ago
  
  8408b45a
Sep 08, 2022
- Maintain static OOB count internally requiring explicit acknowledging reset. · ae2f76c3
  Thomas B. Preußer authored 2 years ago
  
  ae2f76c3
Sep 07, 2022
- ZynqBuild: use AXI port width from part map · c4fad13b
  Felix Jentzsch authored 2 years ago
  
  c4fad13b
Aug 26, 2022
- VVAU: add weightstream width helper · a258b803
  aziz bahri authored 2 years ago
  
  Signed-off-by: aziz bahri <azizb@amd.com>
  a258b803
Aug 25, 2022
- [rtlsim] add custom variant of axis_infrastructure.vh · e7d58388
  Yaman Umuroglu authored 2 years ago
  
  e7d58388
- [Build] add option (enabled) to keep impl_style=vivado for rtlsim · e1d09b95
  Yaman Umuroglu authored 2 years ago
  
  e1d09b95
- [rtlsim] experimental support for impl_style=vivado FIFO and DWC sim · 0b158c2e
  Yaman Umuroglu authored 2 years ago
  
  0b158c2e
Aug 24, 2022
- Restructure, basic resource estimation · f46e2d0a
  Felix Jentzsch authored 2 years ago
  
  f46e2d0a
Aug 22, 2022
- [HLSCustomOp] Adding ap_none interface string · 2afe6ece
  auphelia authored 2 years ago
  
  2afe6ece
Aug 19, 2022
- [IP stitch] make new lookup layer output external · e73a0719
  auphelia authored 2 years ago
  
  e73a0719
Aug 18, 2022
- [Streamline] Updating the transformation to check if the input is in the expected format. · 5dcc89cb
  Le Blevec authored 2 years ago
  
  5dcc89cb
Aug 15, 2022
- [Eltwise] use struct member fxn to workaround HLS pipeline style bug · 2139cb95
  Yaman Umuroglu authored 2 years ago
  
  2139cb95
Aug 11, 2022
- Add IRQ signalling output for input bounds violation (to be externalized). · 4c04af8d
  Thomas B. Preußer authored 2 years ago
  
  4c04af8d
Aug 10, 2022
- [Eltwise] reflect latest hlslib updates · 2c629052
  Yaman Umuroglu authored 2 years ago
  
  2c629052
Aug 09, 2022
- [LookUp layer] Fix typo in pragma insertion · 162d0f26
  auphelia authored 2 years ago
  
  162d0f26
- [LookUp layer] Change hls implementation of LU external · 5ade63a9
  auphelia authored 2 years ago
  
  5ade63a9
Jul 26, 2022
- [Downsample] add 1D downsample support + conversion · b9ac8183
  Yaman Umuroglu authored 2 years ago
  
  b9ac8183
Jul 25, 2022
- [Downsample] reflect changes to HLS kernel name change · 07f43817
  Yaman Umuroglu authored 2 years ago
  
  now with 2D
  07f43817
Jul 22, 2022
- [VVAU] bugfix in weight reps for node-by-node rtlsim · 8c894ed5
  Yaman Umuroglu authored 2 years ago
  
  8c894ed5
- [VVAU] binaryXnorMode support (untested) · 206f4002
  Yaman Umuroglu authored 2 years ago
  
  206f4002
- [InferVVAU] add suport for setting mem_mode at conversion time · 87529826
  Yaman Umuroglu authored 2 years ago
  
  87529826