ZynqBuild: use AXI port width from part map (c4fad13b) · Commits · streichg / Finn · GitLab

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c4fad13b

Commit c4fad13b authored 2 years ago by Felix Jentzsch

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ZynqBuild: use AXI port width from part map

parent df9aa4a4

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src/finn/transformation/fpgadataflow/make_zynq_proj.py 3 additions, 2 deletions

src/finn/transformation/fpgadataflow/make_zynq_proj.py

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