From c4fad13b60402962d3b43887da13fd18cf239a60 Mon Sep 17 00:00:00 2001
From: Felix Jentzsch <felix.jentzsch@upb.de>
Date: Wed, 7 Sep 2022 10:03:32 +0200
Subject: [PATCH] ZynqBuild: use AXI port width from part map
---
src/finn/transformation/fpgadataflow/make_zynq_proj.py | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/finn/transformation/fpgadataflow/make_zynq_proj.py b/src/finn/transformation/fpgadataflow/make_zynq_proj.py
index a589cb039..f48566326 100644
--- a/src/finn/transformation/fpgadataflow/make_zynq_proj.py
+++ b/src/finn/transformation/fpgadataflow/make_zynq_proj.py
@@ -45,7 +45,7 @@ from finn.transformation.fpgadataflow.insert_dwc import InsertDWC
from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO
from finn.transformation.fpgadataflow.insert_iodma import InsertIODMA
from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
-from finn.util.basic import make_build_dir, pynq_part_map
+from finn.util.basic import make_build_dir, pynq_native_port_width, pynq_part_map
from . import templates
@@ -320,6 +320,7 @@ class ZynqBuild(Transformation):
):
super().__init__()
self.fpga_part = pynq_part_map[platform]
+ self.axi_port_width = pynq_native_port_width[platform]
self.period_ns = period_ns
self.platform = platform
self.enable_debug = enable_debug
@@ -330,7 +331,7 @@ class ZynqBuild(Transformation):
model = model.transform(InferDataLayouts())
# prepare at global level, then break up into kernels
prep_transforms = [
- InsertIODMA(64),
+ InsertIODMA(self.axi_port_width),
InsertDWC(),
Floorplan(),
CreateDataflowPartition(partition_model_dir=self.partition_model_dir),
--
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