[CustomOp] Change name of checksum axilite interface

src/finn/custom_op/fpgadataflow/checksum.py

@@ -329,5 +329,5 @@ class CheckSum(HLSCustomOp):
     def get_verilog_top_module_intf_names(self):
         intf_names = super().get_verilog_top_module_intf_names()
         # expose axilite interface
-        intf_names["axilite"] = ["s_axi_checksum"]
+        intf_names["axilite"] = ["s_axilite_checksum"]
         return intf_names