[Transform] minor assertion fixes in InsertFIFO and InsertIODMA

src/finn/transformation/fpgadataflow/insert_fifo.py

@@ -159,7 +159,7 @@ class InsertFIFO(Transformation):
             # insert FIFO as last node, except when last node is DMA
             if (
                 graph.node[-1].op_type != "StreamingFIFO"
-                and graph.node[0].op_type != "IODMA"
+                and graph.node[-1].op_type != "IODMA"
             ):
                 n = graph.node[-1]
                 assert (

src/finn/transformation/fpgadataflow/insert_iodma.py

@@ -81,8 +81,8 @@ class InsertIODMA(Transformation):
                 # check if tensor is NHWC
                 assert (
                     model.get_tensor_layout(graph_out_name) == DataLayout.NHWC
-                    or model.get_tensor_layout(graph_in_name) == DataLayout.NC
-                ), "Data layout of tensors must be NHWC or NC"
+                    or model.get_tensor_layout(graph_out_name) == DataLayout.NC
+                ), "Data layout of output tensor must be NHWC or NC"
                 out_shape = model.get_tensor_shape(graph_out_name)
                 out_dtype = model.get_tensor_datatype(graph_out_name)
                 # determine the feasible interface width
@@ -120,7 +120,7 @@ class InsertIODMA(Transformation):
                 assert (
                     model.get_tensor_layout(graph_in_name) == DataLayout.NHWC
                     or model.get_tensor_layout(graph_in_name) == DataLayout.NC
-                ), "Data layout of tensors must be NHWC or NC"
+                ), "Data layout of input tensor must be NHWC or NC"
                 in_shape = model.get_tensor_shape(graph_in_name)
                 in_dtype = model.get_tensor_datatype(graph_in_name)
                 # determine the feasible interface width