Commits · d4e91a1987fb8c3bbb0af38749a98d4a30b7ef57 · streichg / Finn · GitLab

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Sep 20, 2022
- [InsertDWC] use impl_style=vivado if widths not divisible · d4e91a19
  Yaman Umuroglu authored 2 years ago
  
  d4e91a19
- Merge branch 'feature/rtlsim-vivado-ip' of github.com:Xilinx/finn into feature/rtlsim-vivado-ip · 84a6e9b3
  Yaman Umuroglu authored 2 years ago
  
  84a6e9b3
- [FIFO] instead of fixed-depth large FIFO in sim, use tensor size · 6ccc9499
  Yaman Umuroglu authored 2 years ago
  
  6ccc9499
- [FIFO] instead of fixed-depth large FIFO in sim, use tensor size · 20e4613f
  Yaman Umuroglu authored 2 years ago
  
  20e4613f
Sep 19, 2022
- [FIFO] use hw maxcount monitoring in InsertAndSetFIFODepths · 81f010b8
  Yaman Umuroglu authored 2 years ago
  
  81f010b8
- [FIFO] add hw maxcount tracking to rtl FIFOs with opt attribute · e8f7c756
  Yaman Umuroglu authored 2 years ago
  
  e8f7c756
- Merge branch 'feature/lookup_bounds' into feature/rtlsim-vivado-ip · 6ce1f50d
  Yaman Umuroglu authored 2 years ago
  
  6ce1f50d
- [Deps] update QONNX · dd95873c
  Yaman Umuroglu authored 2 years ago
  
  dd95873c
- Merge branch 'dev' into feature/rtlsim-vivado-ip · a6f79304
  Yaman Umuroglu authored 2 years ago
  
  a6f79304
Sep 15, 2022
- Merge pull request #656 from Xilinx/deps/update-qonnx-version · 1e37d920
  auphelia authored 2 years ago
  
  Update QONNX to latest version
  Unverified
  
  1e37d920
Sep 09, 2022
- [pre-commit] Run pre-commit on lookup layer file · 91e3df89
  auphelia authored 2 years ago
  
  91e3df89
- Rebalanced lookup implementation code to go mostly into header file. · 8408b45a
  Thomas B. Preußer authored 2 years ago
  
  8408b45a
- Match requested II with achievable one. · 8ac23b16
  Thomas B. Preußer authored 2 years ago
  
  8ac23b16
Sep 08, 2022
- Maintain static OOB count internally requiring explicit acknowledging reset. · ae2f76c3
  Thomas B. Preußer authored 2 years ago
  
  ae2f76c3
Aug 25, 2022
- [rtlsim] add custom variant of axis_infrastructure.vh · e7d58388
  Yaman Umuroglu authored 2 years ago
  
  e7d58388
- [Build] add option (enabled) to keep impl_style=vivado for rtlsim · e1d09b95
  Yaman Umuroglu authored 2 years ago
  
  e1d09b95
- [rtlsim] experimental support for impl_style=vivado FIFO and DWC sim · 0b158c2e
  Yaman Umuroglu authored 2 years ago
  
  0b158c2e
- [Deps] update pyverilator and verilator · c50b3482
  Yaman Umuroglu authored 2 years ago
  
  c50b3482
- [Deps] update pyverilator · 8268ec25
  Yaman Umuroglu authored 2 years ago
  
  8268ec25
Aug 22, 2022
- [HLSCustomOp] Adding ap_none interface string · 2afe6ece
  auphelia authored 2 years ago
  
  2afe6ece
Aug 19, 2022
- Merge pull request #668 from Xilinx/feature/manual-verilator-install · df9aa4a4
  auphelia authored 2 years ago
  
  Clone and install particular version of Verilator
  Unverified
  
  df9aa4a4
- Merge pull request #670 from Xilinx/feature/lookup_bounds_irq · fe9cd7db
  auphelia authored 2 years ago
  
  WIP: IRQ Signalling for Input Bounds Violation (to be externalized)
  Unverified
  
  fe9cd7db
- [IP stitch] make new lookup layer output external · e73a0719
  auphelia authored 2 years ago
  
  e73a0719
Aug 15, 2022
- [Deps] manually clone and install particular verilator version · aa228f23
  Yaman Umuroglu authored 2 years ago
  
  aa228f23
Aug 11, 2022
- Add IRQ signalling output for input bounds violation (to be externalized). · 4c04af8d
  Thomas B. Preußer authored 2 years ago
  
  4c04af8d
Aug 09, 2022
- [LookUp layer] Fix typo in pragma insertion · 162d0f26
  auphelia authored 2 years ago
  
  162d0f26
- [LookUp layer] Change hls implementation of LU external · 5ade63a9
  auphelia authored 2 years ago
  
  5ade63a9
Aug 08, 2022
- [Deps] update QONNX to latest version · 8aad25b0
  Yaman Umuroglu authored 2 years ago
  
  Unverified
  
  8aad25b0
Aug 01, 2022
- Lookup through external memory with input bounds checking. · 98aeb90c
  Thomas B. Preußer authored 2 years ago
  
  98aeb90c
Jul 29, 2022
- Merge pull request #647 from Xilinx/feature/builder_verbose · 09bec2fe
  auphelia authored 2 years ago
  
  [Build] New flag "verbose" to control build_dataflow verbosity
  Unverified
  
  09bec2fe
- Merge branch 'dev' into feature/builder_verbose · ffa1b3db
  auphelia authored 2 years ago
  
  ffa1b3db
- Merge pull request #646 from Xilinx/fix/qonnx_quant_conv_bias · a13faced
  auphelia authored 2 years ago
  
  Improvements to QONNX -> FINN-ONNX conversion
  Unverified
  
  a13faced
Jul 27, 2022
- Merge pull request #651 from fionnodonohoe-xlnx/dev · 1aca8432
  auphelia authored 2 years ago
  
  [actions] Update precommit version to work with Act
  Unverified
  
  1aca8432
- [actions] Update precommit version to work with Act · ee76eebb
  Fionn O'Donohoe authored 2 years ago
  
  Signed-off-by: Fionn O'Donohoe <fionno@xilinx.com>
  ee76eebb
Jul 26, 2022
- [Tests] Remove saving of .onnx files in tests · 94c18458
  auphelia authored 2 years ago
  
  94c18458
- Merge branch 'dev' into fix/qonnx_quant_conv_bias · 6495cf87
  auphelia authored 2 years ago
  
  6495cf87
- Merge pull request #645 from Xilinx/feature/streamline_improvements · 30be9f95
  auphelia authored 2 years ago
  
  Improvements to streamlining transformations
  Unverified
  
  30be9f95
Jul 25, 2022
- Merge branch 'dev' into feature/streamline_improvements · 268dc5a4
  auphelia authored 2 years ago
  
  268dc5a4
- Merge pull request #642 from Xilinx/feature/workflow_fix · 15673ceb
  auphelia authored 2 years ago
  
  [actions] Update quicktest workflow to new docker setup
  Unverified
  
  15673ceb
- [tests] temporarily exclude mobilenet qonnx test · 1bf72b16
  auphelia authored 2 years ago
  
  1bf72b16