Commits · cd4af94805f6ee6fb4c0c391dbb3e874ed7df53a · streichg / Finn · GitLab

Snippets Groups Projects

To receive notifications about scheduled maintenance, please subscribe to the mailing-list gitlab-operations@sympa.ethz.ch. You can subscribe to the mailing-list at https://sympa.ethz.ch

Jan 16, 2023
- [FIFO] use at least 2 samples also for convnets for cppsim fifo insertion · cd4af948
  Yaman Umuroglu authored 2 years ago
  
  cd4af948
Jan 11, 2023
- [QONNX] make valid_predecessor_op_type a method, fallback to QuantIdentityHandler · 54283158
  Yaman Umuroglu authored 2 years ago
  
  54283158
Jan 10, 2023
- [Util] Change np.int to np.int_ · 5ad48be5
  auphelia authored 2 years ago
  
  5ad48be5
Jan 09, 2023
- [DataPacking] Delete check for np.str · 1b8bf757
  auphelia authored 2 years ago
  
  1b8bf757
Dec 30, 2022
- [Docs] Fix docstrings in modules · fe6dca92
  auphelia authored 2 years ago
  
  fe6dca92
Dec 19, 2022
- [HLSCustomOp] single-source + prep util fxns for node-by-node rtlsim · e809dab5
  Yaman Umuroglu authored 2 years ago
  
  e809dab5
- [Util] refactor verilator prep into two functions · 2c5d07fa
  Yaman Umuroglu authored 2 years ago
  
  2c5d07fa
Dec 13, 2022
- [Util] remove redundant code from pyverilator utils · fd9a8541
  Yaman Umuroglu authored 2 years ago
  
  fd9a8541
Dec 08, 2022
- [VitisBuild] Reverse check for node name in ipgen and add prefix for node names in vitis build · 5bfdc0e0
  auphelia authored 2 years ago
  
  5bfdc0e0
Nov 16, 2022
- [fix-comments]: in/outFIFODepth renamed to in/outFIFODepths · ea7518e2
  mmrahorovic authored 2 years ago
  
  ea7518e2
Nov 13, 2022

[FIFO] bugfixes+improvements in verilator fifosim template · c8b5368d

Yaman Umuroglu authored 2 years ago

- move input token counting to after clock tick
- introduce separate tracker for last seen output
- introduce (disabled by default) vcd tracing capabilities

c8b5368d

Nov 10, 2022
- [FIFO] improve C++ FIFO sizing template · 8fe057cc
  Yaman Umuroglu authored 2 years ago
  
  8fe057cc
- [FIFO] also generate compilation script for C++ FIFO sizing · 9f8cf74b
  Yaman Umuroglu authored 2 years ago
  
  9f8cf74b
Nov 01, 2022
- [Streamline/Absorb] Reorder insertion/rewire of new trn node · c3083929
  auphelia authored 2 years ago
  
  c3083929
- [Convert] skip streaming eltwise conversion if static inputs · a8343b2d
  Yaman Umuroglu authored 2 years ago
  
  a8343b2d
Oct 27, 2022
- [CustomOp] Add dtype functions to StreamingFIFO · ad6319d5
  auphelia authored 2 years ago
  
  ad6319d5
Oct 24, 2022
- [CustomOp] Delete stream depth pragmas for in/out streams in MVAU and VVAUs · 5d8a0260
  auphelia authored 2 years ago
  
  5d8a0260
Oct 21, 2022
- [Transform] Extend inFIFODepths for extw nodes · c7c15b7c
  auphelia authored 2 years ago
  
  c7c15b7c
Oct 07, 2022
- [EltWise] Change order for node attribute update · a799fe85
  auphelia authored 2 years ago
  
  a799fe85
- [EltWise] Add node attribute for inFIFODepths · 01a62e7f
  auphelia authored 2 years ago
  
  01a62e7f
Oct 06, 2022
- [Refactor] Minor fixes on code · c0dc4af4
  auphelia authored 2 years ago
  
  c0dc4af4
- [CustomOp] Update fmpadding to new hls code · 4c0978e8
  auphelia authored 2 years ago
  
  4c0978e8
Oct 05, 2022
- [CustomOp] Remove overwriting of default FIFO sizes · 72ded22a
  auphelia authored 2 years ago
  
  72ded22a
- [CustomOps] Add missing indices in shape/datatype fcts · 392052b1
  auphelia authored 2 years ago
  
  392052b1
Oct 04, 2022
- [Util] Add comment about usage of axis infrastructure vh · 1ce5af77
  auphelia authored 2 years ago
  
  1ce5af77
- [Stitch] explicitly mark finn_design as top level · acefb525
  Yaman Umuroglu authored 2 years ago
  
  acefb525
Sep 29, 2022
- [FIFO] don't round-up sizes to 2^x, StreamingFIFO does it dynamically · efcc83a4
  Yaman Umuroglu authored 2 years ago
  
  efcc83a4
- [FIFO] small bugfix in input txn counting · 8f6a22ac
  Yaman Umuroglu authored 2 years ago
  
  8f6a22ac
Sep 28, 2022
- [Build] enable using C++ fifosim for rtlsim perf measurement · 59b19dd3
  Yaman Umuroglu authored 2 years ago
  
  59b19dd3
- [FIFO] keep perf metric dict keys consistent in C++ fifo sim · 8c5f1aaa
  Yaman Umuroglu authored 2 years ago
  
  8c5f1aaa
- Revert "Revert "Merge branch 'feature/rtlsim-vivado-ip' into feature/new-fifo-sizing-residual"" · 04217956
  Yaman Umuroglu authored 2 years ago
  
  This reverts commit fc9e880a.
  04217956
- Revert "Revert "Merge branch 'feature/rtlsim-vivado-ip' into feature/new-fifo-sizing-residual"" · 9c6651f7
  Yaman Umuroglu authored 2 years ago
  
  This reverts commit fc9e880a.
  9c6651f7
Sep 27, 2022
- [FIFO] add new build option to enable C++-based FIFO sizing · 56057926
  Yaman Umuroglu authored 2 years ago
  
  56057926
- [FIFO] add new verilator_fifosim util function to call C++ rtlsim · f9d86f40
  Yaman Umuroglu authored 2 years ago
  
  f9d86f40
- [FIFO] C++ template for faster rtlsim with verilator · 8bfedbe8
  Yaman Umuroglu authored 2 years ago
  
  8bfedbe8
Sep 26, 2022
- [customOp] Temp. reverse changes to checksum axilite interface name · 584f0fb5
  auphelia authored 2 years ago
  
  584f0fb5
Sep 23, 2022
- [customOp] Fix typo in eltwise customOp · edf0a91e
  auphelia authored 2 years ago
  
  edf0a91e
- [CustomOp] Add comments to convinputgen rtl · 77f07339
  auphelia authored 2 years ago
  
  77f07339
Sep 22, 2022
- [Style] Minor style fixes to added components · fdb00bb5
  auphelia authored 2 years ago
  
  fdb00bb5
- [Refactor] fix fifo depths property for concat layers at conversion time · 5b1b2ebe
  Yaman Umuroglu authored 2 years ago
  
  5b1b2ebe