[VitisBuild] Apply SLR and memory bank constraints during Vitis Linking

Merge branch 'feature/apply_slr_mem_constraints' of https://github.com/quetric/finn into quetric-feature/apply_slr_mem_constraints

Make linking optional

note: SDP isn't a "proper" fpgadataflow op as it's not derived
from HLSCustomOp, but still better to have it here instead of
in finn-base

Changes to board access for end2end tests

Refactor and test external weights support