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Commit 2804949c authored by Mirzam98's avatar Mirzam98
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[fpgadataflow]: changed imports after RLT/HLS-related utils split

parent e68d7a3a
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......@@ -12,7 +12,7 @@ gecho () {
# checkout the correct dependency repo commits
# the repos themselves are cloned in the Dockerfile
FINN_BASE_COMMIT=8908c6a3f6674c4fa790954bd41c23ee5bf053df
FINN_BASE_COMMIT=94beb27de0decb58d31555823860a24da5f09c5a
BREVITAS_COMMIT=aff49758ec445d77c75721c7de3091a2a1797ca8
CNPY_COMMIT=4e8810b1a8637695171ed346ce68f6984e585ef4
HLSLIB_COMMIT=2e49322d1bbc4969ca293843bda1f3f9c05456fc
......
......@@ -38,11 +38,11 @@ from finn.util.basic import (
roundup_to_integer_multiple,
get_rtlsim_trace_depth,
)
from finn.util.fpgadataflow import (
IPGenBuilder,
from finn.util.pyverilator import (
pyverilate_get_liveness_threshold_cycles,
rtlsim_multi_io,
)
from finn.util.hls import CallHLS
from . import templates
try:
......@@ -310,11 +310,11 @@ class HLSCustomOp(CustomOp):
return []
def ipgen_singlenode_code(self):
"""Builds the bash script for ip generation using the IPGenBuilder from
finn.util.fpgadataflow."""
"""Builds the bash script for ip generation using the CallHLS from
finn.util.hls."""
node = self.onnx_node
code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
builder = IPGenBuilder()
builder = CallHLS()
builder.append_tcl(code_gen_dir + "/hls_syn_{}.tcl".format(node.name))
builder.set_ipgen_path(code_gen_dir + "/project_{}".format(node.name))
builder.build(code_gen_dir)
......
......@@ -39,8 +39,8 @@ from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP
from finn.transformation.fpgadataflow.insert_dwc import InsertDWC
from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO
from finn.transformation.general import GiveUniqueNodeNames, GiveReadableTensorNames
from finn.util.fpgadataflow import pyverilate_stitched_ip, is_fpgadataflow_node
from finn.util.pyverilator import reset_rtlsim, toggle_clk
from finn.util.fpgadataflow import is_fpgadataflow_node
from finn.util.pyverilator import pyverilate_stitched_ip, reset_rtlsim, toggle_clk
def reset_implementation(node):
......
......@@ -52,7 +52,7 @@ from finn.util.basic import (
alveo_part_map,
alveo_default_platform,
)
from finn.util.fpgadataflow import pyverilate_stitched_ip
from finn.util.pyverilator import pyverilate_stitched_ip
from finn.util.test import load_test_checkpoint_or_skip
from finn.transformation.fpgadataflow.synth_ooc import SynthOutOfContext
from finn.transformation.infer_data_layouts import InferDataLayouts
......
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