Commits · 9187e2475ea5ef90fd03202502be3d1621a48534 · streichg / Finn · GitLab

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Sep 26, 2022
- [customOp] Temp. reverse changes to checksum axilite interface name · 584f0fb5
  auphelia authored 2 years ago
  
  584f0fb5
Sep 23, 2022
- [customOp] Fix typo in eltwise customOp · edf0a91e
  auphelia authored 2 years ago
  
  edf0a91e
- [CustomOp] Add comments to convinputgen rtl · 77f07339
  auphelia authored 2 years ago
  
  77f07339
Sep 22, 2022
- [Style] Minor style fixes to added components · fdb00bb5
  auphelia authored 2 years ago
  
  fdb00bb5
Sep 16, 2022
- Address reviewer comments · 5e0e8989
  Felix Jentzsch authored 2 years ago
  
  5e0e8989
Sep 09, 2022
- Lint fix · dfb42854
  Felix Jentzsch authored 2 years ago
  
  dfb42854
- Move parallel impl. to different branch, cleanup · 57f9fecd
  Felix Jentzsch authored 2 years ago
  
  57f9fecd
Sep 07, 2022
- ZynqBuild: use AXI port width from part map · c4fad13b
  Felix Jentzsch authored 2 years ago
  
  c4fad13b
Aug 26, 2022
- VVAU: add weightstream width helper · a258b803
  aziz bahri authored 2 years ago
  
  Signed-off-by: aziz bahri <azizb@amd.com>
  a258b803
Aug 24, 2022
- Restructure, basic resource estimation · f46e2d0a
  Felix Jentzsch authored 2 years ago
  
  f46e2d0a
Aug 18, 2022
- [Streamline] Updating the transformation to check if the input is in the expected format. · 5dcc89cb
  Le Blevec authored 2 years ago
  
  5dcc89cb
Aug 15, 2022
- [Eltwise] use struct member fxn to workaround HLS pipeline style bug · 2139cb95
  Yaman Umuroglu authored 2 years ago
  
  2139cb95
Aug 10, 2022
- [Eltwise] reflect latest hlslib updates · 2c629052
  Yaman Umuroglu authored 2 years ago
  
  2c629052
Jul 22, 2022
- [VVAU] bugfix in weight reps for node-by-node rtlsim · 8c894ed5
  Yaman Umuroglu authored 2 years ago
  
  8c894ed5
- [VVAU] binaryXnorMode support (untested) · 206f4002
  Yaman Umuroglu authored 2 years ago
  
  206f4002
- [InferVVAU] add suport for setting mem_mode at conversion time · 87529826
  Yaman Umuroglu authored 2 years ago
  
  87529826
- [VVAU] port mem_mode=decoupled support from MVAU · e5114ef0
  Yaman Umuroglu authored 2 years ago
  
  e5114ef0
Jul 21, 2022
- [Eltwise] also cover Sub inference and layer tests · 2b516a95
  Yaman Umuroglu authored 2 years ago
  
  2b516a95
- [Eltwise] register op and fix bugs · c5214879
  Yaman Umuroglu authored 2 years ago
  
  c5214879
- [CustomOp] first sketch for StreamingEltwise · 214612ff
  Yaman Umuroglu authored 2 years ago
  
  214612ff
- [ToHLS] draft a InferStreamingEltwiseAbsDiff conversion · 341a8a3e
  Yaman Umuroglu authored 2 years ago
  
  341a8a3e
Jul 20, 2022
- [Streamline] bugfix in MoveLinearPastEltwiseAdd · b76b79eb
  Yaman Umuroglu authored 2 years ago
  
  b76b79eb
- [HLSCustomOp] set target_dir to code_gen_dir if empty · e056b638
  auphelia authored 2 years ago
  
  e056b638
- [QONNX] Remove forking act. restriction for QONNX->FINN-ONNX, works fine · cc643866
  Yaman Umuroglu authored 2 years ago
  
  cc643866
- [Streamline] simplify and improve AbsorbConsecutiveTransposes · a8bb9754
  Yaman Umuroglu authored 2 years ago
  
  a8bb9754
Jul 19, 2022
- [Streamline] allow MoveOpPastFork to copy attributes, impl for Transpose · cbdc575e
  Yaman Umuroglu authored 2 years ago
  
  cbdc575e
- [Build] New flag "verbose" to control build_dataflow verbosity · b70659cb
  Yaman Umuroglu authored 2 years ago
  
  b70659cb
- [QONNX] remove no-fork restriction for QONNX->FINN-ONNX conversion · 84669619
  Yaman Umuroglu authored 2 years ago
  
  84669619
Jul 14, 2022
- [Upsample] add support for 1D upsampling · c9e49ed0
  Yaman Umuroglu authored 2 years ago
  
  c9e49ed0
- [HLSCustomOp] add optional target_dir arg for inp2npy · 362601ed
  Yaman Umuroglu authored 2 years ago
  
  362601ed
- Revert "Merge pull request #637 from Xilinx/dev" · 963fde53
  auphelia authored 2 years ago
  
  This reverts commit fe4a150c, reversing changes made to c98c2211.
  963fde53
- Revert "Merge branch 'main' into dev" · 78f6538e
  auphelia authored 2 years ago
  
  This reverts commit ed0e9698, reversing changes made to 734d1bd4.
  78f6538e
Jul 13, 2022
- [QONNX] use conv output shape for conv layer conversion · e55cc05e
  Yaman Umuroglu authored 2 years ago
  
  e55cc05e
- Fix linting · 090394e0
  Felix Jentzsch authored 2 years ago
  
  090394e0
- Fix OOC synth, add System Verilog support · 1e80caff
  Felix Jentzsch authored 2 years ago
  
  1e80caff
- Fix FIFO OOC synth · b5dccf0f
  Felix Jentzsch authored 2 years ago
  
  b5dccf0f
Jul 12, 2022
- Fixes for tests, ooc synth, clocking · 7fd6a640
  Felix Jentzsch authored 2 years ago
  
  7fd6a640
- FINN-13: Change default U250 platform to align with 2022.1 supported platforms · b1445a16
  Fionn O'Donohoe authored 2 years ago
  
  Signed-off-by: Fionn O'Donohoe <fionno@xilinx.com>
  b1445a16
- [Test] fix Mb/s -> MB/s in throughput end2end test · 9578bbc7
  Yaman Umuroglu authored 2 years ago
  
  9578bbc7
- [Driver] add missing init.py files to generated folder, fix MB typo · 10f60496
  Yaman Umuroglu authored 2 years ago
  
  10f60496