Commits · 7fd6a640d4702f82e330effa27e37edd2b07c1bb · streichg / Finn

Jul 12, 2022
- Fixes for tests, ooc synth, clocking · 7fd6a640
  Felix Jentzsch authored 2 years ago
  
  7fd6a640
Jul 05, 2022
- Adapt to upcoming FINN release · 53ffa343
  Felix Jentzsch authored 2 years ago
  
  53ffa343
- Improve Systemverilog, extend tests · 3a2a8508
  Felix Jentzsch authored 2 years ago
  
  3a2a8508
Jun 13, 2022
- Cleanup and fixes · 34f82112
  Felix Jentzsch authored 2 years ago
  
  34f82112
Jun 12, 2022
- Add conventional implementation style for out_width <= in_width · 0ae77fe7
  Felix Jentzsch authored 2 years ago
  
  0ae77fe7
Mar 23, 2022
- Add RAM buffer component · 0d2a549c
  Felix Jentzsch authored 3 years ago
  
  0d2a549c
Mar 22, 2022
- Replace microprogramming with controller · 0f866f1e
  Felix Jentzsch authored 3 years ago
  
  0f866f1e
Jan 31, 2022
- Basic MMV in/out implementation for a special 1D case · 748049db
  Felix Jentzsch authored 3 years ago
  
  748049db
Jan 25, 2022
- Basic custom_op integration, fixed AXIS handshake · 888d69c3
  Felix Jentzsch authored 3 years ago
  
  888d69c3
Nov 24, 2021
- Initial prototype · cac1ea3a
  Felix Jentzsch authored 3 years ago
  
  cac1ea3a

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