Commits · 72bc7b37662f2a780c2e9320c689fd703b29ab43 · streichg / Finn · GitLab

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Sep 10, 2020
- [Refactor] ReplaceVerilogRelPaths called automatically · 1ca32bb6
  Yaman Umuroglu authored 4 years ago
  
  1ca32bb6
Aug 11, 2020
- [Refactor] sim_cycles -> cycles_rtlsim · b214052b
  Yaman Umuroglu authored 4 years ago
  
  b214052b
- [Test] use node.name to index into expected cycles dict · 008a8e4a
  Yaman Umuroglu authored 4 years ago
  
  008a8e4a
Jul 27, 2020
- [Test] Add exp cycles test for streamingfclayer · f8bbb4a5
  auphelia authored 4 years ago
  
  f8bbb4a5
Jul 11, 2020
- [Test] add rtlsim to large-depth decoupled fclayer test name · 365d4327
  Yaman Umuroglu authored 4 years ago
  
  so that we can run it with the correct parallelization method in the test suite
  365d4327
Jul 03, 2020
- Added external weights option to StreamingFCLayer · 6147c2c2
  Lucian Petrica authored 4 years ago
  
  6147c2c2
May 14, 2020
- [Test] mark some more tests with pytest.mark.vivado · 5a02740d
  Yaman Umuroglu authored 4 years ago
  
  5a02740d
- [Test] add vivado pytest marker · cde32f03
  Yaman Umuroglu authored 4 years ago
  
  cde32f03
- [Test] add slow marker to most slow-running tests · 52d8e6da
  Yaman Umuroglu authored 4 years ago
  
  52d8e6da
May 07, 2020
- [Refactor] fix remaining npysim -> cppsim · 837b6696
  Yaman Umuroglu authored 4 years ago
  
  837b6696
- [Refactor] rename HLSSynth_IPGen to HLSSynthIP · 5e630834
  Yaman Umuroglu authored 4 years ago
  
  5e630834
- [Refactor] rename CodeGen_ipgen to PrepareIP · 130c1462
  Yaman Umuroglu authored 4 years ago
  
  130c1462
- [Refactor] rename Compile to CompileCppSim · 61b39409
  Yaman Umuroglu authored 4 years ago
  
  61b39409
- [Refactor] CodeGen_npysim is renamed to PrepareCppSim · 7f1f280e
  Yaman Umuroglu authored 4 years ago
  
  7f1f280e
Apr 27, 2020
- [Test] add PrepareRTLSim call to additional fclayer test · 919d1f3c
  Yaman Umuroglu authored 4 years ago
  
  919d1f3c
- [StreamingFC] also switch to prepared rtlsim for fclayer · 0992b96a
  Yaman Umuroglu authored 4 years ago
  
  slight difference from others: needs ReplaceVerilogRelPaths
  0992b96a
Apr 22, 2020
- [Test] Add new test for streaming fclayer decoupled mode with mh=mw=128 · fa1d6f7b
  auphelia authored 4 years ago
  
  fa1d6f7b
Mar 31, 2020
- [Test] grow matrix size and large int dtype for StreamingFC test · f19183cf
  Yaman Umuroglu authored 5 years ago
  
  f19183cf
Mar 19, 2020
- [Test] Add mem_mode "decoupled to rtlsim tests of fclayer" · a4092629
  auphelia authored 5 years ago
  
  a4092629
Mar 13, 2020
- [Test] Add mem mode as pytest variable for rtlsim · 66584769
  auphelia authored 5 years ago
  
  66584769
Mar 10, 2020
- [Streamingfc & Test] Commit after clean-up by pre-commit · d69fa33b
  auphelia authored 5 years ago
  
  d69fa33b
- [Test] Add test cases for decoupled mode · 7ce8bc77
  auphelia authored 5 years ago
  
  7ce8bc77
Mar 06, 2020
- [Test] Add test for mem_mode "decoupled" · fd0639b6
  auphelia authored 5 years ago
  
  fd0639b6
- [Streaming FC & test] added experimental dimension fliiping · fa01c039
  auphelia authored 5 years ago
  
  fa01c039
Mar 05, 2020
- [StreamingFC & Test] Add option for weight streamers (npysim) · 6faafc0e
  auphelia authored 5 years ago
  
  6faafc0e
Feb 28, 2020
- [License] add license header to all sources · e000cd02
  Yaman Umuroglu authored 5 years ago
  
  e000cd02
Feb 24, 2020
- [Test] extend the range of FC rtlsim test params · 846a8e0f
  Yaman Umuroglu authored 5 years ago
  
  846a8e0f
Feb 18, 2020
- [Test] Delete clean up from fpgadataflow tests · e7c52abe
  auphelia authored 5 years ago
  
  e7c52abe
Feb 12, 2020
- [All files] Change every occurence of sim mode to exec mode · 1bb9a45f
  auphelia authored 5 years ago
  
  1bb9a45f
Feb 07, 2020
- [Test] separate rtlsim and npysim tests for fclayer · 5cf31c18
  Yaman Umuroglu authored 5 years ago
  
  5cf31c18
Feb 06, 2020
- [Refactor] move utils to own module, remove backend module · f59844d5
  Yaman Umuroglu authored 5 years ago
  
  f59844d5
Jan 30, 2020
- [Test] better pass condition for hls_synth_res_estimation pass · e18571c0
  Yaman Umuroglu authored 5 years ago
  
  e18571c0
- [Test] add comment regarding splitting up into several tests · 000d916d
  Yaman Umuroglu authored 5 years ago
  
  000d916d
Jan 29, 2020
- [Test] Added hls synthesis resource estimation test in fclayer test · ff7686d1
  auphelia authored 5 years ago
  
  ff7686d1
Jan 27, 2020
- [Execution] rtlsim functionality in fclayer cleaned with pre-commit · f588b786
  auphelia authored 5 years ago
  
  f588b786
- [Execution] Added input and output data processing to rtlsim functionality in execution of fclayer · 45d32194
  auphelia authored 5 years ago
  
  45d32194
Jan 09, 2020
- [Code Generation - IP and Test] First draft of IP generation of fclayer · 7d72077e
  auphelia authored 5 years ago
  
  7d72077e
Jan 07, 2020
- [code generation] Added "_npysim" to all involved files · 1db41884
  auphelia authored 5 years ago
  
  1db41884
Dec 06, 2019
- [StreamingFC] calculate wmem/tmem, introduce no_act attribute · cdeaec9c
  Yaman Umuroglu authored 5 years ago
  
  cdeaec9c
- [Test] use binaryXnorMode feature to test bipolar by bipolar · 83f7deeb
  Yaman Umuroglu authored 5 years ago
  
  83f7deeb