tests/fpgadataflow/test_fpgadataflow_fclayer.py · 0992b96a463c1611b9f249a767a006b8e52a2183 · streichg / Finn · GitLab

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4 years ago
0992b96a
[StreamingFC] also switch to prepared rtlsim for fclayer · 0992b96a
Yaman Umuroglu authored 4 years ago
```
slight difference from others: needs ReplaceVerilogRelPaths
```
0992b96a

History
[StreamingFC] also switch to prepared rtlsim for fclayer
Yaman Umuroglu authored 4 years ago
```
slight difference from others: needs ReplaceVerilogRelPaths
```