[Transformation] Add warning if chosen clock period could lead to failure due to clock divider constraints

[Transformation and Test] Add option to adjust clock frequency in ipstitch and when making the pynq project get fclk from the metadata properties. Change tfc w1a1 test to test new feature

use None in util fxn to indicate no file output

[HLSCustomOp] Refactoring fpgadataflow custom ops by adding comments and adding two functions to base class

HLS streaming nodes already have small FIFOs at i/o