Skip to content
Snippets Groups Projects
Commit 514ea68e authored by Yaman Umuroglu's avatar Yaman Umuroglu
Browse files

[rtlsim] Pass trace depth when building pyverilator

parent 9d70ef40
No related branches found
No related tags found
No related merge requests found
Hide whitespace changes
Inline Side-by-side
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment