From 514ea68e0d04e47bed548988a6cc96477830e71e Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Fri, 1 May 2020 21:12:12 +0100
Subject: [PATCH] [rtlsim] Pass trace depth when building pyverilator
---
src/finn/custom_op/fpgadataflow/__init__.py | 8 +++++++-
src/finn/util/fpgadataflow.py | 7 +++++--
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py
index 9a6f66087..8579fdfba 100644
--- a/src/finn/custom_op/fpgadataflow/__init__.py
+++ b/src/finn/custom_op/fpgadataflow/__init__.py
@@ -31,7 +31,12 @@ import numpy as np
import os
import subprocess
from finn.custom_op import CustomOp
-from finn.util.basic import CppBuilder, make_build_dir, roundup_to_integer_multiple
+from finn.util.basic import (
+ CppBuilder,
+ make_build_dir,
+ roundup_to_integer_multiple,
+ get_rtlsim_trace_depth,
+)
from finn.util.fpgadataflow import (
IPGenBuilder,
pyverilate_get_liveness_threshold_cycles,
@@ -128,6 +133,7 @@ class HLSCustomOp(CustomOp):
code_gen_dir, self.onnx_node.name
)
],
+ trace_depth=get_rtlsim_trace_depth(),
)
# save generated lib filename in attribute
self.set_nodeattr("rtlsim_so", sim.lib._name)
diff --git a/src/finn/util/fpgadataflow.py b/src/finn/util/fpgadataflow.py
index e84532d8d..7a404cd53 100644
--- a/src/finn/util/fpgadataflow.py
+++ b/src/finn/util/fpgadataflow.py
@@ -33,7 +33,7 @@ try:
from pyverilator import PyVerilator
except ModuleNotFoundError:
PyVerilator = None
-from finn.util.basic import get_by_name, make_build_dir
+from finn.util.basic import get_by_name, make_build_dir, get_rtlsim_trace_depth
class IPGenBuilder:
@@ -87,7 +87,10 @@ def pyverilate_stitched_ip(model):
top_verilog = model.get_metadata_prop("wrapper_filename")
build_dir = make_build_dir("pyverilator_ipstitched_")
sim = PyVerilator.build(
- top_verilog, verilog_path=all_verilog_dirs, build_dir=build_dir
+ top_verilog,
+ verilog_path=all_verilog_dirs,
+ build_dir=build_dir,
+ trace_depth=get_rtlsim_trace_depth(),
)
return sim
--
GitLab