* Floorplanning support in vitis builds

* Various fixes for floorplanning

* removed partition definition - moved to finn-base

* Add some attribute/argument documentation

* Added transform to set mem modes

* Add transform to set folding (SIMD/PE)

* Implemented resource allocation transform and test

* Reverted to version in dev

* Updated expected resource counts in res estimate test

* Added URAM and DSP resource estimates; changed FC layer resType to lut/dsp, made it optional, and made lut the default

* Correct handling of URAM

* Fixed resource estimation for fc layer

* Fixed uram estimation in SWU

* Fixed res estimate test

* Added resource estimation to VVAU, and changed resType to same pattern in FClayer; fixed DSP estimation in FClayer

* Fixes for VVAU resource estimation

* Updated SWU memory estimate; modified folding transform for correct depthwise SWU folding

* Moved folding transforms out of PR branch

* Removed files added by mistake in merge

* Fixed test

* [Deps, Refactor] update finn-base, move create.py back into finn

* [Deps] update finn-base to get optional, restricted-value attributes

* [HLSCustomOp] specify allowed values for HLSCustomOps where appropriate

* [Deps] update finn-base and Brevitas

Co-authored-by: Yaman Umuroglu <maltanar@gmail.com>

* [Refactor] use getCustomOp instead of direct registry access

* [Refactor] move HLSCustomOp base to own file

* [Refactor] register all HLSCustomOps in new style

* [Refactor] use correct domain for custom ops acc. to new style

* [Deps] update finn-base to get new-style customop domains

* [Refactor] more domain fixes

* [Test] fix ipstitch expected io values in rtlsim

* [Deps] update finn-base and brevitas

* [Docs] link to CustomOp reorg PR

* [CustomOp] groundwork for decoupled Thresholding op

* [Thresholding] more decoupled mode preparation

- new attributes for "weight" (really threshold) datatype + n_steps
- move thres datatype into acc minimization function and call in convert_to_hls
- other helper functions

* [Refactor] add make_weight_file for Thresholding layer + wire up

* [Threshold] first attempt at Thresholding_Stream_Batch

* [Threshold] wire up more decoupled functionality, add test

test does not yet pass for multi-PE

* [Threshold] use 2 layers of slicers, all decoupled cppsim passes now

* [Threshold] more decoupled fixes, most rtlsim tests pass

* [Threshold] add unroll to decoupled thresholding, remove unused vars

* [ConvertToHLS] allow specifying mem_mode in InferThresholdingLayer

* [Threshold] expose interfaces for runtime weight writing

* [Test] add runtime threshold test

not yet passing

* [Threshold] use std::less_equal also for decoupled

* [Threshold] use flipped PE axis for decoupled-more rtl thresholds

* [Test] runtime threshold reading works

* [Test] runtime writable thresholds test working

* [ConvertToHLS] fix threshold shape

* [StreamingFC] introduce make_weight_file helper function

not yet wired into the rest of the class

* [Test] use make_weight_file helper in runtime weight test

* [Test] make runtime weight test work with different aspect ratio

* [Refactor] StreamingFC: use make_weight_file in generate_params

Improve throughput of Data width converter

Enable and test writable weights in decoupled mode

some discrepancies between vivado and HLS here so sometimes AXI
lite signals appear as e.g. ifname_AREADY whereas other times it
is ifname_aready

Merge branch 'feature/writable_weights' of https://github.com/quetric/finn into quetric-feature/writable_weights

Merge branch 'feature/writable_weights' of https://github.com/quetric/finn into quetric-feature/writable_weights

Merge branch 'feature/writable_weights' of https://github.com/quetric/finn into quetric-feature/writable_weights

AXI lite utils for PyVerilator