Merge pull request #237 from Xilinx/feature/pyverilator_axilite
AXI lite utils for PyVerilator
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- src/finn/qnn-data/verilog/myadd/myadd_myadd.v 118 additions, 0 deletionssrc/finn/qnn-data/verilog/myadd/myadd_myadd.v
- src/finn/qnn-data/verilog/myadd/myadd_myadd_control_s_axi.v 357 additions, 0 deletionssrc/finn/qnn-data/verilog/myadd/myadd_myadd_control_s_axi.v
- src/finn/transformation/fpgadataflow/set_fifo_depths.py 4 additions, 7 deletionssrc/finn/transformation/fpgadataflow/set_fifo_depths.py
- src/finn/util/pyverilator.py 124 additions, 0 deletionssrc/finn/util/pyverilator.py
- tests/util/test_pyverilator.py 96 additions, 0 deletionstests/util/test_pyverilator.py
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