Support Vivado AXIS infrastructure IP in rtlsim

build_dataflow verification improvements

Lookup through external memory with input bounds checking

Support 1D Downsample

Decoupled mode support for VVAU

MakeScaleResizeNHWC tranformation

Feature/axi info

Bump protobuf from 3.20.1 to 3.20.2

Bumps [protobuf](https://github.com/protocolbuffers/protobuf) from 3.20.1 to 3.20.2.
- [Release notes](https://github.com/protocolbuffers/protobuf/releases)
- [Changelog](https://github.com/protocolbuffers/protobuf/blob/main/generate_changelog.py)
- [Commits](https://github.com/protocolbuffers/protobuf/compare/v3.20.1...v3.20.2

)

---
updated-dependencies:
- dependency-name: protobuf
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>

StreamingEltwise layer 

[MakeScaleResizeNHWC] Update on test script to correct errors. Now also verifying that the transform actually happened rather than just fonctionnality

ZynqBuild: use AXI port width from part map

RTL ConvolutionInputGenerator