Merge pull request #685 from Xilinx/feature/rtlsim-vivado-ip
Support Vivado AXIS infrastructure IP in rtlsim
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- docker/Dockerfile.finn 1 addition, 1 deletiondocker/Dockerfile.finn
- fetch-repos.sh 2 additions, 2 deletionsfetch-repos.sh
- finn-rtllib/memstream/hdl/Q_srl.v 6 additions, 1 deletionfinn-rtllib/memstream/hdl/Q_srl.v
- src/finn/builder/build_dataflow_config.py 4 additions, 0 deletionssrc/finn/builder/build_dataflow_config.py
- src/finn/builder/build_dataflow_steps.py 37 additions, 33 deletionssrc/finn/builder/build_dataflow_steps.py
- src/finn/custom_op/fpgadataflow/streamingfifo.py 10 additions, 0 deletionssrc/finn/custom_op/fpgadataflow/streamingfifo.py
- src/finn/custom_op/fpgadataflow/templates.py 3 additions, 0 deletionssrc/finn/custom_op/fpgadataflow/templates.py
- src/finn/qnn-data/verilog/custom_axis_infrastructure.vh 346 additions, 0 deletionssrc/finn/qnn-data/verilog/custom_axis_infrastructure.vh
- src/finn/transformation/fpgadataflow/insert_dwc.py 7 additions, 0 deletionssrc/finn/transformation/fpgadataflow/insert_dwc.py
- src/finn/transformation/fpgadataflow/set_fifo_depths.py 36 additions, 30 deletionssrc/finn/transformation/fpgadataflow/set_fifo_depths.py
- src/finn/util/pyverilator.py 45 additions, 6 deletionssrc/finn/util/pyverilator.py
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