Commits · 0fb57af5ca46657970309fa5a9599adee356d933 · streichg / Finn

Dec 01, 2022
- [RTL SWG] Rework parallel-output implementation style · 0fb57af5
  Felix Jentzsch authored 2 years ago
  
  0fb57af5
Oct 27, 2022
- [SWGG] improve HDL code · 3d002f7e
  Felix Jentzsch authored 2 years ago
  
  3d002f7e
Oct 24, 2022
- [SWGG] incorporate Yaman's changes + small fixes · 83550c64
  Felix Jentzsch authored 2 years ago
  
  83550c64
Oct 04, 2022
- FIFO] bugfix post-reset ibp condition on Q_srl · 1a4166c9
  Yaman Umuroglu authored 2 years ago
  
  1a4166c9
Sep 27, 2022
- [FIFO] SystemVerilog -> Verilog fix in Q_srl.v · a8d3fb6c
  Yaman Umuroglu authored 2 years ago
  
  a8d3fb6c
Sep 26, 2022
- [FIFO] SystemVerilog -> Verilog fix in Q_srl.v · dc830f11
  Yaman Umuroglu authored 2 years ago
  
  dc830f11
Sep 22, 2022
- [Style] Minor style fixes to added components · fdb00bb5
  auphelia authored 2 years ago
  
  fdb00bb5
- Working initial implementation · ecb5a7e3
  Felix Jentzsch authored 2 years ago
  
  ecb5a7e3
Sep 19, 2022
- [FIFO] add hw maxcount tracking to rtl FIFOs with opt attribute · e8f7c756
  Yaman Umuroglu authored 2 years ago
  
  e8f7c756
Sep 16, 2022
- Address reviewer comments · 5e0e8989
  Felix Jentzsch authored 2 years ago
  
  5e0e8989
Sep 09, 2022
- Move parallel impl. to different branch, cleanup · 57f9fecd
  Felix Jentzsch authored 2 years ago
  
  57f9fecd
Aug 24, 2022
- Restructure, basic resource estimation · f46e2d0a
  Felix Jentzsch authored 2 years ago
  
  f46e2d0a
Jul 14, 2022
- Revert "Merge pull request #637 from Xilinx/dev" · 963fde53
  auphelia authored 2 years ago
  
  This reverts commit fe4a150c, reversing changes made to c98c2211.
  963fde53
Jul 12, 2022
- Fixes for tests, ooc synth, clocking · 7fd6a640
  Felix Jentzsch authored 2 years ago
  
  7fd6a640
Jul 05, 2022
- Adapt to upcoming FINN release · 53ffa343
  Felix Jentzsch authored 2 years ago
  
  53ffa343
- Improve Systemverilog, extend tests · 3a2a8508
  Felix Jentzsch authored 2 years ago
  
  3a2a8508
Jun 29, 2022
- [Refactor] Change copyright header · 7750fbb0
  auphelia authored 2 years ago
  
  7750fbb0
Jun 28, 2022
- [Pre-commit] pre-commit fixes of axi-info tcl script and Jenkinsfile · fa2401a8
  auphelia authored 2 years ago
  
  fa2401a8
Jun 17, 2022
- Hotfix: Instance name for axi_info instantiation. · 889ba2ce
  Thomas B. Preußer authored 2 years ago
  
  889ba2ce
- Hotfix: Instance name for axi_info instantiation. · dd704a6c
  Thomas B. Preußer authored 2 years ago
  
  dd704a6c
Jun 13, 2022
- Cleanup and fixes · 34f82112
  Felix Jentzsch authored 2 years ago
  
  34f82112
Jun 12, 2022
- Add conventional implementation style for out_width <= in_width · 0ae77fe7
  Felix Jentzsch authored 2 years ago
  
  0ae77fe7
May 31, 2022
- [finn-rtllib] Update ip for axi-info · 989fbdae
  auphelia authored 2 years ago
  
  989fbdae
May 30, 2022
- Fixed signature composition. · e88a0295
  Thomas B. Preußer authored 2 years ago
  
  e88a0295
May 25, 2022
- [finn rtllib] Add updated packaged ip for axi_info · d47a5599
  auphelia authored 2 years ago
  
  d47a5599
- axi_info read not to block upon out-of-bounds accesses. · 5d0da833
  Thomas B. Preußer authored 2 years ago
  
  5d0da833
May 24, 2022
- [Refactor] move checksum files to under custom_hls · dac25880
  Yaman Umuroglu authored 2 years ago
  
  dac25880
May 23, 2022
- Packaged IP infrastructure for axi_info. · f7173c99
  Thomas B. Preußer authored 2 years ago
  
  f7173c99
- [HLSCustomOp] generate separate sync/sim .dat files for decoupled · 833be8e1
  Yaman Umuroglu authored 2 years ago
  
  833be8e1
May 13, 2022
- Component to expose a compiled-in constant info space on AXI-lite. · 92c0171a
  Thomas B. Preußer authored 2 years ago
  
  92c0171a
May 12, 2022
- Corrected copyright. · bc572eef
  Thomas B. Preußer authored 2 years ago
  
  bc572eef
May 05, 2022
- Generic top-level macro customizable through command-line defines. · d20837db
  Thomas B. Preußer authored 2 years ago
  
  d20837db
May 04, 2022
- Prototype for checksumming over stream data. · 232464c7
  Thomas B. Preußer authored 2 years ago
  
  232464c7
Mar 23, 2022
- Add RAM buffer component · 0d2a549c
  Felix Jentzsch authored 3 years ago
  
  0d2a549c
Mar 22, 2022
- Replace microprogramming with controller · 0f866f1e
  Felix Jentzsch authored 3 years ago
  
  0f866f1e
Jan 31, 2022
- Basic MMV in/out implementation for a special 1D case · 748049db
  Felix Jentzsch authored 3 years ago
  
  748049db
Jan 25, 2022
- Basic custom_op integration, fixed AXIS handshake · 888d69c3
  Felix Jentzsch authored 3 years ago
  
  888d69c3
Nov 30, 2021
- [Vitis] minor fixes for 2021.1 and Versal Prime parts · 91eaf3b1
  Yaman Umuroglu authored 3 years ago
  
  91eaf3b1
Nov 24, 2021
- Initial prototype · cac1ea3a
  Felix Jentzsch authored 3 years ago
  
  cac1ea3a
Sep 30, 2021
- Updated achritecture families to all current types, minus the CPLDs · bda18b3d
  john authored 3 years ago
  
  bda18b3d

Admin message