[Transform] always call ReplaceVerilogRelPaths before PrepareRTLSim (dbc65ece) · Commits · streichg / Finn · GitLab

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dbc65ece

Commit dbc65ece authored 4 years ago by Yaman Umuroglu

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[Transform] always call ReplaceVerilogRelPaths before PrepareRTLSim

parent 3ddafb64

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src/finn/transformation/fpgadataflow/prepare_rtlsim.py 7 additions, 1 deletion

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