[Transform] always call ReplaceVerilogRelPaths before PrepareRTLSim

src/finn/transformation/fpgadataflow/prepare_rtlsim.py

@@ -28,7 +28,9 @@
 
 import finn.custom_op.registry as registry
 from finn.util.fpgadataflow import is_fpgadataflow_node
-
+from finn.transformation.fpgadataflow.replace_verilog_relpaths import (
+    ReplaceVerilogRelPaths,
+)
 from finn.transformation import NodeLocalTransformation
 
 try:
@@ -54,6 +56,10 @@ class PrepareRTLSim(NodeLocalTransformation):
     def __init__(self, num_workers=None):
         super().__init__(num_workers=num_workers)
 
+    def apply(self, model):
+        model = model.transform(ReplaceVerilogRelPaths())
+        return super().apply(model)
+
     def applyNodeLocal(self, node):
         op_type = node.op_type
         if is_fpgadataflow_node(node) is True: