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Commit b88c93e3 authored by auphelia's avatar auphelia
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[Transformation] Add warning if chosen clock period could lead to failure due...

[Transformation] Add warning if chosen clock period could lead to failure due to clock divider constraints
parent f7d38d7d
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......@@ -27,7 +27,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
import warnings
import finn.custom_op.registry as registry
from finn.transformation import Transformation
from finn.util.basic import make_build_dir
......@@ -75,6 +75,11 @@ class PrepareIP(Transformation):
super().__init__()
self.fpgapart = fpgapart
self.clk = clk
if float(clk) not in [5.0, 10.0, 20.0]:
warnings.warn(
"""The chosen frequency may lead to failure due to clock divider
constraints."""
)
def apply(self, model):
for node in model.graph.node:
......
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