From b88c93e33dd4d55fefd3eb832b35d6b35bae8c83 Mon Sep 17 00:00:00 2001
From: auphelia <jakobapk@web.de>
Date: Tue, 12 May 2020 11:06:06 +0100
Subject: [PATCH] [Transformation] Add warning if chosen clock period could
lead to failure due to clock divider constraints
---
src/finn/transformation/fpgadataflow/prepare_ip.py | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/finn/transformation/fpgadataflow/prepare_ip.py b/src/finn/transformation/fpgadataflow/prepare_ip.py
index 001827735..dbe52f619 100644
--- a/src/finn/transformation/fpgadataflow/prepare_ip.py
+++ b/src/finn/transformation/fpgadataflow/prepare_ip.py
@@ -27,7 +27,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
-
+import warnings
import finn.custom_op.registry as registry
from finn.transformation import Transformation
from finn.util.basic import make_build_dir
@@ -75,6 +75,11 @@ class PrepareIP(Transformation):
super().__init__()
self.fpgapart = fpgapart
self.clk = clk
+ if float(clk) not in [5.0, 10.0, 20.0]:
+ warnings.warn(
+ """The chosen frequency may lead to failure due to clock divider
+ constraints."""
+ )
def apply(self, model):
for node in model.graph.node:
--
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