Fix FIFO OOC synth

src/finn/transformation/fpgadataflow/create_stitched_ip.py

@@ -535,7 +535,8 @@ class CreateStitchedIP(Transformation):
         # export list of used Verilog files (for rtlsim later on)
         tcl.append(
             "set all_v_files [get_files -filter {USED_IN_SYNTHESIS == 1 "
-            + "&& (FILE_TYPE == Verilog || FILE_TYPE == SystemVerilog)}]"
+            + "&& (FILE_TYPE == Verilog || FILE_TYPE == SystemVerilog "
+            + "|| FILE_TYPE ==\"Verilog Header\")}]"
         )
         v_file_list = "%s/all_verilog_srcs.txt" % vivado_stitch_proj_dir
         tcl.append("set fp [open %s w]" % v_file_list)