From b5dccf0f6aceb84ea0b2f84725e88f6c0a161f9b Mon Sep 17 00:00:00 2001
From: Felix Jentzsch <felix.jentzsch@upb.de>
Date: Wed, 13 Jul 2022 11:35:52 +0200
Subject: [PATCH] Fix FIFO OOC synth
---
src/finn/transformation/fpgadataflow/create_stitched_ip.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
index d52868f5f..35ac736aa 100644
--- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py
+++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
@@ -535,7 +535,8 @@ class CreateStitchedIP(Transformation):
# export list of used Verilog files (for rtlsim later on)
tcl.append(
"set all_v_files [get_files -filter {USED_IN_SYNTHESIS == 1 "
- + "&& (FILE_TYPE == Verilog || FILE_TYPE == SystemVerilog)}]"
+ + "&& (FILE_TYPE == Verilog || FILE_TYPE == SystemVerilog "
+ + "|| FILE_TYPE ==\"Verilog Header\")}]"
)
v_file_list = "%s/all_verilog_srcs.txt" % vivado_stitch_proj_dir
tcl.append("set fp [open %s w]" % v_file_list)
--
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