Fix stitched ip sim, add builder cfg (91a64c2b) · Commits · streichg / Finn · GitLab

Skip to content

GitLab

Explore

Sign in

Primary navigation

Project

F

Finn
- Activity
- Members
- Labels
- Issues
- Issue boards
- Milestones
- Wiki
- Environments
- Terraform modules
- Incidents

Snippets Groups Projects

Admin message

To receive notifications about scheduled maintenance, please subscribe to the mailing-list gitlab-operations@sympa.ethz.ch. You can subscribe to the mailing-list at https://sympa.ethz.ch

91a64c2b

Commit 91a64c2b authored 2 years ago by Felix Jentzsch

Downloads
- Patches
- Plain Diff

Fix stitched ip sim, add builder cfg

parent 53ffa343

No related branches found

No related tags found

No related merge requests found

Changes 4

Hide whitespace changes

Inline Side-by-side

Showing

src/finn/builder/build_dataflow_config.py 4 additions, 0 deletions

src/finn/builder/build_dataflow_config.py
src/finn/builder/build_dataflow_steps.py 4 additions, 1 deletion

src/finn/builder/build_dataflow_steps.py
src/finn/transformation/fpgadataflow/create_stitched_ip.py 2 additions, 2 deletions

src/finn/transformation/fpgadataflow/create_stitched_ip.py
src/finn/util/pyverilator.py 2 additions, 1 deletion

src/finn/util/pyverilator.py

with 12 additions and 4 deletions

Loading

0% Loading or .

You are about to add 0 people to the discussion. Proceed with caution.

Finish editing this message first!

Please register or sign in to comment