From 91a64c2b232ce8639bb5eadc8db745771a359f19 Mon Sep 17 00:00:00 2001
From: Felix Jentzsch <felix.jentzsch@upb.de>
Date: Wed, 6 Jul 2022 13:43:36 +0200
Subject: [PATCH] Fix stitched ip sim, add builder cfg
---
src/finn/builder/build_dataflow_config.py | 4 ++++
src/finn/builder/build_dataflow_steps.py | 5 ++++-
src/finn/transformation/fpgadataflow/create_stitched_ip.py | 4 ++--
src/finn/util/pyverilator.py | 3 ++-
4 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/finn/builder/build_dataflow_config.py b/src/finn/builder/build_dataflow_config.py
index 381dfe91a..eec55e502 100644
--- a/src/finn/builder/build_dataflow_config.py
+++ b/src/finn/builder/build_dataflow_config.py
@@ -258,6 +258,10 @@ class DataflowBuildConfig:
#: Which memory mode will be used for compute layers
default_mem_mode: Optional[ComputeEngineMemMode] = ComputeEngineMemMode.DECOUPLED
+ #: Force inference of RTL ConvolutionInputGenerator over HLS implementation
+ #: If set to False, falls back to the default behavior of InferConvInpGen()
+ force_rtl_conv_inp_gen: Optional[bool] = False
+
#: Which Vitis platform will be used.
#: Only relevant when `shell_flow_type = ShellFlowType.VITIS_ALVEO`
#: e.g. "xilinx_u250_xdma_201830_2"
diff --git a/src/finn/builder/build_dataflow_steps.py b/src/finn/builder/build_dataflow_steps.py
index 59f77650d..e77f17d7c 100644
--- a/src/finn/builder/build_dataflow_steps.py
+++ b/src/finn/builder/build_dataflow_steps.py
@@ -302,7 +302,10 @@ def step_convert_to_hls(model: ModelWrapper, cfg: DataflowBuildConfig):
# needed for convolutions -- TODO always exec?
need_conv = len(model.get_nodes_by_op_type("Im2Col")) > 0
if need_conv:
- model = model.transform(to_hls.InferConvInpGen())
+ if cfg.force_rtl_conv_inp_gen:
+ model = model.transform(to_hls.InferConvInpGen(use_rtl_variant=True))
+ else:
+ model = model.transform(to_hls.InferConvInpGen())
model = model.transform(to_hls.InferStreamingMaxPool())
model = model.transform(RemoveCNVtoFCFlatten())
# get rid of Tranpose -> Tranpose identity seq
diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
index 7c978cf61..d52868f5f 100644
--- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py
+++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
@@ -534,8 +534,8 @@ class CreateStitchedIP(Transformation):
tcl.append("ipx::save_core [ipx::find_open_core %s]" % block_vlnv)
# export list of used Verilog files (for rtlsim later on)
tcl.append(
- "set all_v_files [get_files -filter {FILE_TYPE == Verilog "
- + "&& USED_IN_SYNTHESIS == 1} ]"
+ "set all_v_files [get_files -filter {USED_IN_SYNTHESIS == 1 "
+ + "&& (FILE_TYPE == Verilog || FILE_TYPE == SystemVerilog)}]"
)
v_file_list = "%s/all_verilog_srcs.txt" % vivado_stitch_proj_dir
tcl.append("set fp [open %s w]" % v_file_list)
diff --git a/src/finn/util/pyverilator.py b/src/finn/util/pyverilator.py
index 3396561e0..ee7df3ed5 100644
--- a/src/finn/util/pyverilator.py
+++ b/src/finn/util/pyverilator.py
@@ -74,7 +74,8 @@ def pyverilate_stitched_ip(
# are identical but in multiple directories (regslice_core.v)
# remove duplicates from list by doing list -> set -> list
- all_verilog_files = list(set(filter(lambda x: x.endswith(".v"), all_verilog_srcs)))
+ all_verilog_files = list(set(filter(lambda x: x.endswith(".v") or x.endswith(".sv"),
+ all_verilog_srcs)))
# remove all but one instances of regslice_core.v
filtered_verilog_files = []
--
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