[Test] specify target PYNQ board from env.var, add part mapping

Dockerfile

@@ -25,6 +25,7 @@ ENV PYTHONPATH "${PYTHONPATH}:/workspace/brevitas_cnv_lfc/training_scripts"
 ENV PYTHONPATH "${PYTHONPATH}:/workspace/brevitas"
 ENV PYTHONPATH "${PYTHONPATH}:/workspace/pyverilator"
 ENV PYNQSHELL_PATH "/workspace/PYNQ-HelloWorld/boards"
+ENV PYNQ_BOARD "Pynq-Z1"
 
 ARG GID
 ARG GNAME

src/finn/util/basic.py

@@ -8,6 +8,11 @@ import numpy as np
 
 from finn.core.datatype import DataType
 
+# mapping from PYNQ board names to FPGA part names
+pynq_part_map = dict()
+pynq_part_map["Ultra96"] = "xczu3eg-sbva484-1-e"
+pynq_part_map["Pynq-Z1"] = "xc7z020clg400-1"
+
 
 def get_finn_root():
     "Return the root directory that FINN is cloned into."

tests/fpgadataflow/test_fpgadataflow_ip_stitch.py

@@ -20,16 +20,11 @@ from finn.util.basic import (
     calculate_signed_dot_prod_range,
     gen_finn_dt_tensor,
     make_build_dir,
+    pynq_part_map,
 )
 
-# TODO control board/part for tests from a global place
-# settings for Ultra96
-# test_fpga_part = "xczu3eg-sbva484-1-e"
-# test_pynq_board = "Ultra96"
-
-# settings for PYNQ-Z1
-test_fpga_part = "xc7z020clg400-1"
-test_pynq_board = "Pynq-Z1"
+test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1")
+test_fpga_part = pynq_part_map[test_pynq_board]
 
 ip_stitch_model_dir = make_build_dir("test_fpgadataflow_ipstitch")