[StreamingDWC] Add dummy npysim path with output = input (3b0a6728) · Commits · streichg / Finn · GitLab

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3b0a6728

Commit 3b0a6728 authored 5 years ago by auphelia

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[StreamingDWC] Add dummy npysim path with output = input

parent fe2dfa99

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src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py 6 additions, 1 deletion

...stom_op/fpgadataflow/streamingdatawidthconverter_batch.py

with 6 additions and 1 deletion

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