From 3b0a67283b7090dc826190d3100f11a81af4dad5 Mon Sep 17 00:00:00 2001
From: auphelia <jakobapk@web.de>
Date: Tue, 31 Mar 2020 15:16:17 +0100
Subject: [PATCH] [StreamingDWC] Add dummy npysim path with output = input
---
.../fpgadataflow/streamingdatawidthconverter_batch.py | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py b/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py
index 8f3546494..54d044bda 100644
--- a/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py
+++ b/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py
@@ -316,7 +316,12 @@ class StreamingDataWidthConverter_Batch(HLSCustomOp):
reshaped_input = reshaped_input.copy()
np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input)
- if mode == "rtlsim":
+ if mode == "npysim":
+ output = np.load(os.path.join(code_gen_dir, "input_0.npy"))
+ output = np.asarray([output], dtype=np.float32).reshape(exp_shape)
+ context[node.output[0]] = output
+
+ elif mode == "rtlsim":
prefixed_top_name = "%s_%s" % (node.name, node.name)
# check if needed file exists
verilog_file = "{}/project_{}/sol1/impl/verilog/{}.v".format(
--
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