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Commit 38e9d5af authored by Yaman Umuroglu's avatar Yaman Umuroglu
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[FIFO] use impl_style=hls for first&last FIFOs to avoid glitch

parent 1c2a1c12
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......@@ -209,13 +209,9 @@ class InsertFIFO(Transformation):
graph.value_info.append(fifo_output_tensor)
model.set_tensor_datatype(fifo_output_tensor.name, dtype)
if (
self.max_qsrl_depth is None
or fifo_depth <= self.max_qsrl_depth
):
impl_style = "rtl"
else:
impl_style = "vivado"
# only use rtl-style FIFOs to avoid simulation bug
# (top-level IOs should not have impl_style=vivado)
impl_style = "rtl"
fifo_node = oh.make_node(
"StreamingFIFO",
......@@ -271,13 +267,9 @@ class InsertFIFO(Transformation):
graph.value_info.append(fifo_input_tensor)
model.set_tensor_datatype(fifo_input_tensor.name, dtype)
if (
self.max_qsrl_depth is None
or fifo_depth <= self.max_qsrl_depth
):
impl_style = "rtl"
else:
impl_style = "vivado"
# only use rtl-style FIFOs to avoid simulation bug
# (top-level IOs should not have impl_style=vivado)
impl_style = "rtl"
fifo_node = oh.make_node(
"StreamingFIFO",
......
......@@ -412,8 +412,13 @@ class InsertAndSetFIFODepths(Transformation):
node_inst = getCustomOp(node)
node_inst.set_nodeattr("depth", depth)
node_inst.set_nodeattr("depth_monitor", 0)
# exception for top-level IO FIFOs which cause a bug in simulation
# (top-level IOs should not have impl_style=vivado)
toplevel_in = node.input[0] in [x.name for x in model.graph.input]
toplevel_out = node.output[0] in [x.name for x in model.graph.output]
toplevel_style_exception = toplevel_in or toplevel_out
# Set FIFO implementation/ram styles
if depth > self.max_qsrl_depth:
if (depth > self.max_qsrl_depth) and (not toplevel_style_exception):
node_inst.set_nodeattr("impl_style", "vivado")
node_inst.set_nodeattr("ram_style", self.vivado_ram_style)
else:
......
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